- 您现在的位置：买卖IC网 > PDF目录17401 > ADP1871-0.6-EVALZ (Analog Devices Inc)BOARD EVAL FOR ADP1871-0.6 PDF资料下载
参数资料
| 型号： | ADP1871-0.6-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADP1871-0.6 |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
Data Sheet
THEORY OF OPERATION
The ADP1870/ADP1871 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by utilizing valley
current-mode control architecture. This allows the ADP1870/
ADP1870/ADP1871
ADP1870/ADP1871, reducing the supply current of the devices
ADP1870/ADP1871
FB
VREG
SS
ADP1871 to drive all N-channel power stages to regulate output
voltages as low as 0.6 V.
COMP/EN
ERROR
AMPLIFIER
0.6V
STARTUP
The ADP1870/ADP1871 have an internal regulator (VREG) for
biasing and supplying power for the integrated MOSFET drivers.
A bypass capacitor should be located directly across the VREG
(Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence
C C
R C
C C2
PRECISION
ENABLE
TO ENABLE
ALL BLOCKS
285mV
is the biasing of the current-sense amplifier, the current-sense
section), the soft start circuit, and the error amplifier.
The current-sense blocks provide valley current information
Figure 66. Release COMP/EN Pin to Enable the ADP1870/ADP1871
COMP/EN
(see the Programming Resistor (RES) Detect Circuit section)
and are a variable of the compensation equation for loop stability
(see the Compensation Network section). The valley current
information is extracted by forcing 0.4 V across the DRVL output
and PGND pin, which generates a current depending on the
resistor across DRVL and PGND in a process performed by the
RES detect circuit. The current through the resistor is used to set
the current-sense amplifier gain. This process takes approximately
800 μs, after which the drive signal pulses appear at the DRVL
and DRVH pins synchronously and the output voltage begins to
rise in a controlled manner through the soft start sequence.
>2.4V
2.4V
1.0V
500mV
285mV
0V
HICCUP MODE INITIALIZED
MAXIMUM CURRENT (UPPER CLAMP)
ZERO CURRENT
USABLE RANGE ONLY AFTER SOFT START
PERIOD IF CONTUNUOUS CONDUCTION
MODE OF OPERATION IS SELECTED.
LOWER CLAMP
PRECISION ENABLE THRESHOLD
35mV HYSTERESIS
The rise time of the output voltage is determined by the soft
start and error amplifier blocks (see the Soft Start section). At
the beginning of a soft start, the error amplifier charges the
external compensation capacitor, causing the COMP/EN pin to
rise above the enable threshold of 285 mV, thus enabling the
ADP1870/ADP1871.
SOFT START
The ADP1870/ADP1871 have digital soft start circuitry, which
involves a counter that initiates an incremental increase in current,
by 1 μA, via a current source on every cycle through a fixed internal
capacitor. The output tracks the ramping voltage by producing
PWM output pulses to the upper-side MOSFET. The purpose is to
limit the in-rush current from the high voltage input supply (V IN )
to the output (V OUT ).
PRECISION ENABLE CIRCUITRY
The ADP1870/ADP1871 employ precision enable circuitry. The
enable threshold is 285 mV typical with 35 mV of hysteresis.
The devices are enabled when the COMP/EN pin is released,
allowing the error amplifier output to rise above the enable
threshold (see Figure 66). Grounding this pin disables the
Figure 67. COMP/EN Voltage Range
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the part from
operating both the upper- and lower-side MOSFETs at extremely
low or undefined input voltage (V IN ) ranges. Operation at an
undefined bias voltage may result in the incorrect propagation
of signals to the high-side power switches. This, in turn, results
in invalid output behavior that can cause damage to the output
devices, ultimately destroying the device tied to the output. The
UVLO level has been set at 2.65 V (nominal).
ON-BOARD LOW DROPOUT REGULATOR
The ADP1870 uses an on-board LDO to bias the internal digital
and analog circuitry. With proper bypass capacitors connected
to the VREG pin (output of internal LDO), this pin also provides
power for the internal MOSFET drivers. It is recommended to
float VREG if VIN is utilized for greater than 5.5 V operation.
The minimum voltage where bias is guaranteed to operate is
2.75 V at VREG.
For applications where VIN is decoupled from VREG, the
minimum voltage at VIN must be 2.9 V. It is recommended that
Rev. B | Page 19 of 44
相关PDF资料 |
PDF描述 |
|---|---|
| GCC15DRYI-S13 | CONN EDGECARD 30POS .100 EXTEND |
| CT11BK50-D | 11" BLACK 50LB CABLE TIE |
| RM-2415S | CONV DC/DC 0.25W 24VIN 15VOUT |
| RBC06DCSH-S288 | CONN EDGECARD 12POS .100 EXTEND |
| RM-2412S | CONV DC/DC 0.25W 24VIN 12VOUT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1871-1.0-EVALZ | 功能描述:BOARD EVAL FOR ADP1871-1.0 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ADP1871ACPZ-0.3-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 10LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1871ACPZ-0.6-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 10LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1871ACPZ-1.0-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 10LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| ADP1871ARMZ-0.3-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 10-MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。