参数资料
型号: ADP1873ARMZ-0.6-R7
厂商: Analog Devices Inc
文件页数: 37/40页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 10-MSOP
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 65%
电源电压: 2.75 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 标准包装
产品目录页面: 792 (CN2011-ZH PDF)
其它名称: ADP1873ARMZ-0.6-R7DKR
Data Sheet
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 4). This plane should only be on the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly
below this plane on Layer 2, Layer 3, or Layer 4. Connect the
negative terminals of all sensitive analog components to the
analog ground plane. Examples of such sensitive analog com-
ponents include the resistor divider’s bottom resistor, the high
frequency bypass capacitor for biasing (0.1 μF), and the
compensation network.
Mount a 1 μF bypass capacitor directly across the VDD pin
(Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 μF should
be tied across the VDD pin (Pin 5) and the GND pin (Pin 4).
POWER SECTION
As shown in Figure 83, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 87). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4
turns on. When Q3/Q4 turns on, the current direction continues to
be maintained (red arrow) as it circles from the bulk capacitor’s
power ground terminal to the output capacitors, through the
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at source
terminals of Q1/Q2 and drain terminals of Q3/Q4, cause large
dV/dts at the SW node.
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components because
ADP1872/ADP1873
SW
VOUT
VIN PGND
Figure 87. Primary Current Pathways During the On State of the Upper-Side
MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)
DIFFERENTIAL SENSING
Because the ADP1872/ADP1873 operate in valley current-
mode control, a differential voltage reading is taken across the
drain and source of the lower-side MOSFET. The drain of the
lower-side MOSFET should be connected as close as possible to
the SW pin (Pin 9) of the IC. Likewise, the source should be
connected as close as possible to the PGND pin (Pin 7) of the
IC. When possible, both of these track lines should be narrow
and away from any other active device or voltage/current paths.
SW
PGND
this is where most sudden changes in flux density occur. When
possible, replicate this pad onto Layer 2 and Layer 3 for thermal
LAYER 1: SENSE LINE FOR SW
(DRAIN OF LOWER MOSFET)
LAYER 1: SENSE LINE FOR PGND
(SOURCE OF LOWER MOSFET)
relief and eliminate any other voltage and current pathways directly
beneath the SW node plane. Populate the SW node plane with
vias, mainly around the exposed pad of the inductor terminal
and around the perimeter of the source of Q1/Q2 and the drain
of Q3/Q4. The output voltage power plane (VOUT) is at the right-
most end of the evaluation board. This plane should be replicated,
descending down to multiple layers with vias surrounding the
inductor terminal and the positive terminals of the output bulk
capacitors. Ensure that the negative terminals of the output
capacitors are placed close to the main power ground (PGND),
as previously mentioned. All of these points form a tight circle
Figure 88. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2)
Differential sensing should also be applied between the
outermost output capacitor to the feedback resistor divider (see
Figure 85 and Figure 86). Connect the positive terminal of the
output capacitor to the top resistor (R T ). Connect the negative
terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current paths.
(component geometry permitting) that minimizes the area of
flux change as the event switches between D and 1 ? D.
Rev. B | Page 37 of 40
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ADP1873ARMZ-1.0-R7 功能描述:IC REG CTRLR BUCK PWM CM 10-MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP(0.300",7.62mm) 包装:管件 产品目录页面:1316 (CN2011-ZH PDF)
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