参数资料
型号: ADP1878ACPZ-0.6-R7
厂商: Analog Devices Inc
文件页数: 23/40页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 14LFCSP
标准包装: 1,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 65%
电源电压: 2.95 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 14-WFDFN 裸露焊盘,CSP
包装: 带卷 (TR)
Data Sheet
is sensed through the counter action upswing of the output
(COMP) of the error amplifier.
The result is a convergence of these two signals (see Figure 78),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes V OUT to transient down, which causes COMP to
transient up and, therefore, shortens the off time. This resulting
increase in frequency during a positive load transient helps to
quickly bring V OUT back up in value and within the regulation
window.
Similarly, a negative load step causes the off time to lengthen in
response to V OUT rising. This effectively increases the inductor
demagnetizing phase, helping to bring V OUT within regulation.
In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.
Because the ADP1878 / ADP1879 have the ability to respond rapidly
to sudden changes in load demand, the recovery period in which
the output voltage settles back to its original steady state operating
point is much quicker than it would be for a fixed frequency
equivalent . Therefore, using a pseudo fixed frequency results in
significantly better load transient performance compared to
using a fixed frequency.
ADP1878/ADP1879
the internal switch is turned on, PGOOD is internally pulled low
when the output voltage via the FB pin is outside this regulation
window.
The power-good window is defined with a typical upper speci-
fication of +90 mV and a lower specification of ?70 mV below
the FB voltage of 600 mV. When an overvoltage event occurs at the
output, there is a typical propagation delay of 12 μs prior to the
deassertion (logic low) of the PGOOD pin. When the output
voltage reenters the regulation window, there is a propagation
delay of 12 μs prior to PGOOD reasserting back to a logic high
state. When the output is outside the regulation window, the
PGOOD open-drain switch is capable of sinking 1 mA of
current and providing 140 mV of drop across this switch. The
user is free to tie the external pull-up resistor (R RES ) to any
voltage rail up to 20 V. The following equation provides the
proper external pull-up resistor value:
140  mV
1  mA
where:
R PGD is the PGOOD external resistor.
V EXT is a user chosen voltage rail.
V EXT
1mA
R PGD
LOAD CURRENT
DEMAND
690mV
+
140mV
PGOOD
FB
600mV
CS AMP
OUTPUT
530mV
ERROR AMP
OUTPUT
VALLEY
TRIP POINTS
Figure 79. Power Good, Output Voltage Monitoring Circuit
OUTPUT OVERVOLTAGE
PWM OUTPUT
f SW
> f SW
FB
690mV
640mV
HYSTERESIS (50mV)
PGOOD DEASSERT
PGOOD
REASSERT
600mV
Figure 78. Load Transient Response Operation
POWER-GOOD MONITORING
The ADP1878 / ADP1879 power-good circuitry monitors the
0V
530mV
SOFT START
PGOOD
ASSERTION
AT POWER-UP
PGOOD
DEASSERTION
AT POWER-DOWN
output voltage via the FB pin. The PGOOD pin is an open-
drain output that can be pulled up by an external resistor to a
VEXT
voltage rail that does not necessarily have to be VREG. When
PGOOD
t PGD
t PGD
t PGD
the internal NMOS switch is in high impedance (off state), this
means that the PGOOD pin is logic high and the output voltage
via the FB pin is within the specified regulation window. When
0V t PGD
Figure 80. Power-Good Timing Diagram, t PGD = 12 μs (Diagram May Look
Disproportionate For Illustration Purposes)
Rev. B | Page 23 of 40
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