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参数资料
| 型号： | ADP2114-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/40页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 3.3V/1.8V |
| 设计资源： | Powering AD9268 with ADP2114 for Increased Efficiency (CN0137) |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 可调 |
| 电流 - 输出： | 4A，2A |
| 输入电压： | 2.75 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz，600kHz，1.2MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP2114 |
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ADP2114
DESIGN EXAMPLE
Data Sheet
( V IN ? V OUT ) V OUT
Δ I L × f SW
The external component selection procedure from the Control
Loop Compensation section is used for this design example.
Table 9. 2-Channel Step-Down DC-to-DC Converter
Requirements
Additional
Parameter Specification Requirements
3.
Select the inductor by using Equation 5.
L = ×
V IN
In Equation 5, V IN = 5 V, V OUT = 3.3 V, ΔI L = 0.3 × I L = 0.6 A,
and f SW = 600 kHz, which results in L = 3.11 μH.
Input Voltage, V IN
Channel 1, V OUT1
Channel 2, V OUT2
Pulse-Skip Feature
5.0 V ±10%
3.3 V, 2 A, 1% V OUT
ripple (p-p)
1.8 V, 2 A, 1% V OUT
ripple (p-p)
Enabled
None
Maximum load step:
1 A to 2 A, 5% droop
maximum
Maximum load step:
1 A to 2 A, 5% droop
maximum
None
Therefore, when L = 3.3 μH (the closest standard value) in
Equation 3, ΔI L = 0.566 A.
Although the maximum output current required is 2 A, the
maximum peak current is 3.3 A under the current limit
condition (see Table 7). Therefore, the inductor should be
rated for 3.3 A of peak current and 3 A of average current
for reliable circuit operation.
C OUT_MIN ?
CHANNEL 1 CONFIGURATION AND COMPONENTS
SELECTION
Complete the following steps to configure Channel 1:
4.
Select the output capacitor by using Equation 8 and
Equation 9.
ΔI L
8 × f SW × ( ΔV RIPPLE - ΔI L × ESR )
V OUT
3
C OUT_MIN ? ΔI OUT_STEP × ? ?
?
f SW × ΔV DROOP
?
?
1.
2.
For the target output voltage, V OUT = 3.3 V, connect the
Because one of the fixed output voltage options is chosen,
the feedback pin (FB1) must be directly connected to the
output of Channel 1, V OUT1 .
Estimate the duty-cycle, D, range. Ideally,
D = (20)
V IN
That gives the duty cycle for the 3.3 V output voltage and
the nominal input voltage of D NOM = 0.66 at V IN = 5.0 V.
? ?
?
Equation 8 is based on the output ripple (ΔV RIPPLE ), and
Equation 9 is for capacitor selection based on the transient
load performance requirements that allow, in this case, 5%
maximum deviation. As previously mentioned, perform
these calculations and choose whatever equation yields the
larger capacitor size.
In this case, the following values are substituted for the
variables in Equation 8 and Equation 9:
V REF
V OUT
The minimum duty cycle, D MIN , for the maximum input
voltage (10% above the nominal) is D MIN = 0.60 at V IN
maximum = 5.5 V
The maximum duty cycle, D MAX , for the minimum input
voltage (10% less than nominal) is D MAX = 0.73 at V IN
minimum = 4.5 V.
However, the actual duty cycle is larger than the calculated
values to compensate for the power losses in the converter.
Therefore, add 5% to 7% at the maximum load.
Based on the estimated duty-cycle range, choose the
switching frequency according to the minimum and
For the Channel 1 V IN = 5 V and V OUT = 3.3 V combination,
choose f SW = 600 kHz with a maximum duty cycle of 0.8.
This frequency option provides the smallest sized solution.
If a higher efficiency is required, choose the 300 kHz option.
However, the PCB footprint area of the converter will be
larger because of the bigger inductor and output capacitors.
5.
ΔI L = 0.566 A
f SW = 600 kHz
ΔV RIPPLE = 33 mV (1% of 3.3 V)
ESR = 3 m? (typical for ceramic capacitors)
ΔI OUT_STEP = 1 A
ΔV DROOP = 0.165 V (5% of 3.3 V)
The output ripple based calculation (see Equation 8) dictates
that C OUT = 4.0 μF, whereas the transient load based
calculation (see Equation 9) dictates that C OUT = 30 μF. To
meet both requirements, choose the latter. As previously
mentioned in the Control Loop Compensation section, the
capacitor value reduces with applied dc bias; therefore, select a
higher value. In this case, the next higher value is 47 μF
with a minimum voltage rating of 6.3 V.
Calculate the feedback loop, compensation component
values by using Equation 15.
H(s) = g M × G CS × × Z COMP (s) × Z FILT (s)
Rev. B | Page 30 of 40
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP2114-EVALZ | 制造商:Analog Devices 功能描述:4A Step-Down DC/DC Converter Evaluation 制造商:Analog Devices 功能描述:ADP2114, DC TO DC CONVERTER, STEP DOWN, EVAL BOARD |
| ADP2116 | 制造商:AD 制造商全称:Analog Devices 功能描述:Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator |
| ADP2116ACPZ-R7 | 功能描述:IC REG BUCK SYNC ADJ 32LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V，1.5V，1.8V，2.5V 输入电压:2.7 V ~ 20 V PWM 型:- 频率 - 开关:- 电流 - 输出:50mA 同步整流器:是 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 包装:带卷 (TR) 供应商设备封装:10-MSOP 裸露焊盘 |
| ADP2116ACPZ-R7 | 制造商:Analog Devices 功能描述:DC/DC CONVERTER IC |
| ADP2116-BL1-EVZ | 功能描述:EVAL BOARD FOR ADP2116 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 标准包装:1 系列:- 主要目的:DC/DC，步降 输出及类型:1，非隔离 功率 - 输出:- 输出电压:3.3V 电流 - 输出:3A 输入电压:4.5 V ~ 28 V 稳压器拓扑结构:降压 频率 - 开关:250kHz 板类型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名称:497-12113STEVAL-ISA094V1-ND |
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