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参数资料
| 型号： | ADP225CP-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADP225 |
| 标准包装： | 1 |
| 系列： | * |
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND ?0.3 V to +6 V
ADJ1, ADJ2, VOUT1, VOUT2 to GND ?0.3 V to VIN
EN1, EN2 to GND ?0.3 V to +6 V
Storage Temperature Range ?65°C to +150°C
Operating Junction Temperature Range ?40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP222 / ADP223 / ADP224 / ADP225 can be damaged when
the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that T J is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance, the
maximum ambient temperature can exceed the maximum limit as
long as the junction temperature is within specification limits.
The junction temperature (T J ) of the device is dependent on the
ambient temperature (T A ), the power dissipation of the device
(P D ), and the junction-to-ambient thermal resistance of the
ADP222/ADP223/ADP224/ADP225
Junction-to-ambient thermal resistance (θ JA ) of the package is
based on modeling and calculation using a 4-layer board. θ JA
is highly dependent on the application and board layout. In
applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value
of θ JA may vary, depending on PCB material, layout, and
environmental conditions. The specified value of θ JA is based
on a 4-layer, 4 in × 3 in, 2? oz copper board, as per JEDEC
standards. For more information, see the AN-772 Application
Note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP) .
Ψ JB is the junction-to-board thermal characterization parameter
with units of °C/W. Ψ JB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information , states that
thermal characterization parameters are not the same as thermal
resistances. Ψ JB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θ JB . Therefore, Ψ JB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make Ψ JB more useful in real-world
applications. Maximum junction temperature (T J ) is calculated
from the board temperature (T B ) and power dissipation (P D )
using the formula
T J = T B + ( P D × Ψ JB )
Refer to JESD51-8 and JESD51-12 for more detailed
information about Ψ JB .
THERMAL RESISTANCE
θ JA and Ψ JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
package (θ JA ). Maximum junction temperature (T J ) is calculated
from the ambient temperature (T A ) and power dissipation (P D )
using the formula
Table 4. Thermal Resistance
Package Type
8-Lead 2 mm × 2 mm LFCSP
θ JA
50.2
θ JC
31.7
Ψ JB
18.2
Unit
°C/W
T J = T A + ( P D × θ JA )
ESD CAUTION
Rev. D | Page 5 of 24
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