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| 型号： | ADP320ACPZ331815R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 1/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3/1.8/1.5V 16LFCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V，1.8V，1.5V |
| 输入电压： | 1.8 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.11V @ 200mA，-，- |
| 稳压器数量： | 3 |
| 电流 - 输出： | 200mA（最小值） |
| 电流 - 限制（最小）： | 250mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-WQ（3x3） |
| 包装： | 标准包装 |
| 其它名称： | ADP320ACPZ331815R7DKR |
Triple, 200 mA, Low Noise,
High PSRR Voltage Regulator
ADP320
FEATURES
TYPICAL APPLICATION CIRCUITS
Bias voltage range (VBIAS): 2.5 V to 5.5 V
LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V
2.5V TO VBIAS
ADP320
VBIAS
Three 200 mA low dropout voltage regulators
16-lead, 3 mm × 3 mm LFCSP
Initial accuracy: ±1%
Stable with 1 μF ceramic output capacitors
No noise bypass capacitor required
3 independent logic controlled enables
Over current and thermal protection
Key specifications
5.5V
1.8V TO VIN1/VIN2
5.5V
+
+
1μF
1μF
EN1
EN2
OFF
OFF
ON
ON
LDO 1
EN LD1
VBIAS
LDO 2
EN LD2
VOUT1
+
1μF
VOUT2
+
1μF
High PSRR
VBIAS
76 dB PSRR up to 1 kHz
70 dB PSRR 10 kHz
60 dB PSRR at 100 kHz
1.8V TO VIN3
5.5V
+
1μF
EN3
OFF
ON
LDO 3
EN LD3
VOUT3
+
1μF
40 dB PSRR at 1 MHz
Low output noise
29 μV rms typical output noise at V OUT = 1.2 V
55 μV rms typical output noise at V OUT = 2.8 V
Excellent transient response
Low dropout voltage: 110 mV @ 200 mA load
85 μA typical ground current at no load, all LDOs enabled
100 μs fast turn-on circuit
Guaranteed 200 mA output current per regulator
?40°C to +125°C junction temperature
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
GENERAL DESCRIPTION
The ADP320 200 mA triple output LDO combines high PSRR, low
noise, low quiescent current, and low dropout voltage in a voltage
regulator ideally suited for wireless applications with demanding
performance and board space requirements.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP320 triple LDO extend the battery life of
portable devices. The ADP320 triple LDO maintains power supply
rejection greater than 60 dB for frequencies as high as 100 kHz
while operating with a low headroom voltage. The ADP320 triple
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
GND
Figure 1. Typical Application Circuit
LDO offers much lower noise performance than competing LDOs
without the need for a noise bypass capacitor.
The ADP320 triple LDO is available in a miniature 16-lead
3 mm × 3 mm LFCSP package and is stable with tiny 1 μF ±30%
ceramic output capacitors, resulting in the smallest possible board
area for a wide variety of portable power needs.
The ADP320 triple LDO is available in output voltage combin-
ations ranging from 0.8 V to 3.3 V and offers over current and
thermal protection to prevent damage in adverse conditions.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ?2010–2011 Analog Devices, Inc. All rights reserved.
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