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参数资料
| 型号： | ADP320ACPZ331815R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3/1.8/1.5V 16LFCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V，1.8V，1.5V |
| 输入电压： | 1.8 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.11V @ 200mA，-，- |
| 稳压器数量： | 3 |
| 电流 - 输出： | 200mA（最小值） |
| 电流 - 限制（最小）： | 250mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-WQ（3x3） |
| 包装： | 标准包装 |
| 其它名称： | ADP320ACPZ331815R7DKR |
ADP320
THEORY OF OPERATION
The ADP320 triple LDO is a low quiescent current, low dropout
linear regulator that operates from 1.8 V to 5.5 V on VIN1/VIN2
and VIN3 and provides up to 200 mA of current from each
output. Drawing a low 250 μA quiescent current (typical) at full
load makes the ADP320 triple LDO ideal for battery-operated
portable equipment. Shutdown current consumption is typically
100 nA.
Optimized for use with small 1 μF ceramic capacitors, the
ADP320 triple LDO provides excellent transient performance.
Internally, the ADP320 triple LDO consist of a reference,
three error amplifiers, three feedback voltage dividers, and
three PMOS pass transistors. Output current is delivered
via the PMOS pass device, which is controlled by the error
amplifier. The error amplifier compares the reference voltage
with the feedback voltage from the output and amplifies the
difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to flow and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate
VIN1/VIN2
VOUT1
of the PMOS device is pulled higher, allowing less current to
flow and decreasing the output voltage.
VBIAS
EN1
EN2
EN3
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
SHUTDOWN
VOUT1
SHUTDOWN
VOUT2
SHUTDOWN
VOUT3
OVERCURRENT
OVERCURRENT
0.5V
REF
0.5V
REF
VOUT2
The ADP320 triple LDO is available in multiple output voltage
options ranging from 0.8 V to 3.3 V. The ADP320 triple LDO
uses the EN1, EN2, and EN3 enable pins to enable and disable
the VOUT1/VOUT2/VOUT3 pins under normal operating
conditions. When the enable pins are high, VOUT1/VOUT2/
VOUT3 turn on; when enable pins are low, VOUT1/VOUT2/
VOUT3 turn off. For automatic startup, the enable pins can be
tied to VBIAS.
VIN3
VOUT3
GND
OVERCURRENT
0.5V
REF
Figure 41. Internal Block Diagram
Rev. A | Page 14 of 20
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