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参数资料
| 型号： | ADP320ACPZ331815R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3/1.8/1.5V 16LFCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V，1.8V，1.5V |
| 输入电压： | 1.8 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.11V @ 200mA，-，- |
| 稳压器数量： | 3 |
| 电流 - 输出： | 200mA（最小值） |
| 电流 - 限制（最小）： | 250mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-WQ（3x3） |
| 包装： | 标准包装 |
| 其它名称： | ADP320ACPZ331815R7DKR |
ADP320
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP320 triple LDO is designed for operation with small,
space-saving ceramic capacitors, but the parts function with
most commonly used capacitors as long as care is taken in
regards to the effective series resistance (ESR) value. The ESR
of the output capacitor affects stability of the LDO control loop.
A minimum of 0.70 μF capacitance with an ESR of 1 ? or less
is recommended to ensure stability of the ADP320 triple LDO.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP320 triple LDO to
large changes in the load current. Figure 42 show the transient
response for an output capacitance value of 1 μF.
I LOAD1
1
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN1/VIN2, VIN3, and
VBIAS to GND reduces the circuit sensitivity to the PCB layout,
especially when long input traces or high source impedance are
encountered. If an output capacitance greater than 1 μF is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor may be used with the ADP320
triple LDO, as long as the capacitor meets the minimum capacit-
ance and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with a different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
of an 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
2
3
4
V OUT1
V OUT2
V OUT3
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the ?40°C to +85°C tempera-
ture range and is not a function of the package or voltage rating.
1.2
CH1 100mA
? B
W
CH2 50mV
B
W
M40μs
A CH1
44mA
CH3 10mV
B
W
CH4 10mV
B
W
T 9.8%
1.0
Figure 42. Output Transient Response,
I LOAD1 = 1 mA to 200 mA, I LOAD2 = 1 mA, I LOAD3 = 1 mA,
CH1 = I LOAD1 , CH2 = V OUT1 , CH3 = V OUT2 , CH4 = V OUT3
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
VOLTAGE (V)
Figure 43. Capacitance vs. Voltage Bias Characteristic
Rev. A | Page 15 of 20
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