参数资料
| 型号： | ADS1259BIPWR |
| 厂商： | Texas Instruments |
| 文件页数： | 25/48页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SPI 14KSPS 20TSSOP |
| 标准包装： | 2,000 |
| 位数： | 24 |
| 采样率（每秒）： | 14k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；2 个单端，双极；1 个差分，单极；1 个差分，双极 |
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1
9
17
25
33
41
DRDY
(1)
CS
(2)
SCLK
DOUT
DATAMSB
012h
(8)
DATAMID
DATALSB
CHECKSUM
(5)
DATAMSB
(6)
DIN
(7)
DataReady
NextDataReady
t
UPDATE
(3)
Hi-Z
(4)
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
Data Read Operation in Stop Continuous Mode
As shown in Figure 61, after sending the RDATA
command the data are shifted out on DOUT on the
In Stop Read Data Continuous mode, a read data
rising edges of SCLK. The MSB is clocked out on the
command (RDATA) must be sent for each new data
first rising edge of SCLK. In Gate Control mode,
read operation. New conversion data are ready when
DRDY returns to high on the first falling edge of
DRDY falls low or the DRDY register bit transitions
SCLK. In Pulse Control mode, DRDY remains low
low. The data read operation may then occur. The
until a new conversion is started.
read data command must be sent at least 20 fCLK
cycles before the DRDY falling edge or the data are
The conversion data consist of three or four bytes
incorrect. Do not the read data command during this
(MSB first), depending on whether the checksum byte
time.
is included. The data may be read multiple times by
continuing to shift the data.
(1) In Gate Control mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Control mode, DRDY remains low until the next
conversion is started. The DRDY pin or DRDY register bit can also be polled to determine when data are ready.
(2) CS may be held low.
(3) tUPDATE = 20/fCLK. Do not issue the Read Data opcode during this time.
(4) During this interval, DOUT does not follow DRDY (stop continuous mode).
(5) Optional conversion data checksum.
(6) Optional repeat of previous conversion data.
(7) DIN data are latched on the falling edge of SCLK. Data are output on the rising edges of SCLK.
(8) Read Data command = 012h.
Figure 61. Data Read Operation in STOP Continuous Mode
Copyright
2009–2011, Texas Instruments Incorporated
31
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相关代理商/技术参数 |
参数描述 |
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| ADS1259EVM | 功能描述:数据转换 IC 开发工具 ADS1259 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| ADS1259EVM | 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL |
| ADS1259EVM-PDK | 功能描述:数据转换 IC 开发工具 ADS1259 Perf Demo Kit RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| ADS1259EVM-PDK | 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL |
| ADS1259IPW | 功能描述:模数转换器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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