参数资料
型号: ADS6242IRGZTG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48
封装: 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件页数: 26/76页
文件大小: 3497K
代理商: ADS6242IRGZTG4
www.ti.com
SNR
dBFS
71
72
73
74
75
76
Input Clock Duty Cycle %
83
85
87
89
91
93
35
40
45
50
55
60
65
SFDR
dBc
G032
SNR
SFDR
fIN = 20.1 MHz
76
78
80
82
84
86
88
90
92
0.5
1.0
1.5
2.0
2.5
3.0
SFDR
dBc
SNR
dBFS
68
69
70
71
72
73
74
75
76
Input Clock Amplitude VPP
G031
SNR
SFDR
fIN = 70.1 MHz
fS Sampling Frequency MSPS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
20
40
60
80
100
P
D
Power
Dissipation
W
G033
LVDD
AVDD
Output Code
0
5
10
15
20
25
30
35
40
8179 8180 8181 8182 8183 8184 8185 8186 8187 8188
Occurence
%
G034
RMS (LSB) = 1.054
f Frequency MHz
100
90
80
70
60
50
40
30
20
10
0
50
100
150
200
250
300
CMRR
Common-Mode
Rejection
Ratio
dBc
G018
SNR
dBFS
66
68
70
72
74
76
VVCM VCM Voltage V
80
81
82
83
84
85
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
fIN = 70.1 MHz
External Reference Mode
SFDR
dBc
G035
SNR
SFDR
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6244 (Fs = 105 MSPS) (continued)
All plots are at 25
°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs CLOCK DUTY CYCLE
Figure 36.
Figure 37.
OUTPUT NOISE HISTOGRAM WITH
POWER DISSIPATION vs SAMPLING FREQUENCY
INPUTS TIED TO COMMON-MODE
Figure 38.
Figure 39.
PERFORMANCE IN EXTERNAL REFERENCE MODE
CMRR vs FREQUENCY
Figure 40.
Figure 41.
32
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
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