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| 型号： | ADS6242IRGZTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48 |
| 封装： | 7 X 7 MM, GREEN, PLASTIC, QFN-48 |
| 文件页数： | 76/76页 |
| 文件大小： | 3497K |
| 代理商： | ADS6242IRGZTG4 |
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TIMING SPECIFICATIONS
(1)
SLAS542A – MAY 2007 – REVISED JULY 2007
Typical values are at 25
°C, min and max values are across the full temperature range T
MIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF
(2), I
O = 3.5 mA,
RL = 100
(3), no internal termination, unless otherwise noted.
ADS6245
ADS6244
ADS6243
ADS6242
TEST
PARAMETER
UNIT
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
tJ
Aperture jitter Uncertainty in
the sampling
250
fs rms
instant
Interface: 2-wire, DDR bit clock, 14x serialization
From data
Data setup
cross-over to
tsu
0.35
0.55
0.45
0.65
0.85
0.8
1.1
ns
time(4) (5)(6)
bit clock
cross-over
From bit clock
Data hold
cross-over to
th
0.35
0.58
0.5
0.7
0.9
0.8
1.1
ns
time(4) (5)(6)
data
cross-over
Input clock
rising edge
Clock
tpd_cl
cross-over to
propagation
3.4
4.4
5.4
3.4
4.4
5.4
3.4
4.4
5.4
3.4
4.4
5.4
ns
k
frame clock
delay (6)
rising edge
cross-over
Bit clock
cycle-cycle
350
ps pp
jitter (5)
Frame clock
cycle-cycle
75
ps pp
jitter (5)
Below specifications apply for 5 MSPS
≤ Sampling freq ≤ 125 MSPS and all interface
options
Delay from
input clock
Aperture
rising edge to
tA
1
2
3
1
2
3
1
2
3
1
2
3
ns
delay
the actual
sampling
instant
Aperture
Channel-
delay
channel within
–250
±80
250
–250
±80
250
–250
±80
250
–250
±80
250
ps
variation
same device
Time for a
sample to
ADC Latency
Clock
propagate to
12
(7)
cycles
ADC outputs,
see Figure 1
(1)
Timing parameters are ensured by design and characterization and not tested in production.
(2)
CL is the external single-ended load capacitance between each output pin and ground.
(3)
Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
(4)
Timing parameters are measured at the end of a 2 inch pcb trace (100-
Ω characteristic impedance) terminated by RLand CL.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6)
Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
(7)
Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
listed in Table 28.
Copyright 2007, Texas Instruments Incorporated
9
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