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| 型号： | ADSP-2101BG-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 68PGA |
| 标准包装： | 1 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | 同步串行端口（SSP） |
| 时钟速率： | 25MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 6kB |
| 电压 - 输入/输出： | 5.00V |
| 电压 - 核心： | 5.00V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 68-BEPGA |
| 供应商设备封装： | 68-PGA（27.89x27.89） |
| 包装： | 托盘 |
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ADSP-21xx
–44–
REV. B
TIMING PARAMETERS (ADSP-2103/2162/2164)
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
ADSP-21xx
Memory Specification
Timing Parameter
Timing Parameter Definition
Address Setup to Write Start
tASW
A0–A13, DMS, PMS Setup before WR Low
Address Setup to Write End
tAW
A0–A13, DMS, PMS Setup before WR Deasserted
Address Hold Time
tWRA
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup Time
tDW
Data Setup before WR High
Data Hold Time
tDH
Data Hold after WR High
OE to Data Valid
tRDD
RD Low to Data Valid
Address Access Time
tAA
A0–A13, DMS, PMS, BMS to Data Valid
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相关代理商/技术参数 |
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|---|---|
| ADSP-2101BG-40 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-2101BG-50 | 制造商:Analog Devices 功能描述: |
| ADSP-2101BG-66 | 制造商:AD 制造商全称:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2101BG-80 | 制造商:AD 制造商全称:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2101BGZ-100 | 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 25MHZ 25MIPS 68CPGA - Trays |
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