参数资料
型号: ADSP-21060LCB-133
厂商: Analog Devices Inc
文件页数: 24/64页
文件大小: 0K
描述: IC DSP CONTROLLER 32BIT 225BGA
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: 主机接口,连接端口,串行端口
时钟速率: 33MHz
非易失内存: 外部
芯片上RAM: 512kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 225-BBGA
供应商设备封装: 225-PBGA
包装: 托盘
Rev. F
|
Page 30 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106xs (BRx) or a host processor, both
synchronous and asynchronous (HBR, HBG).
Table 18. Multiprocessor Bus Request and Host Bus Request
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tHBGRCSV
HBG Low to RD/WR/CS Valid1
20 + 5DT/4
ns
tSHBRI
HBR Setup Before CLKIN2
20 + 3DT/4
ns
tHHBRI
HBR Hold After CLKIN2
14 + 3DT/4
ns
tSHBGI
HBG Setup Before CLKIN
13 + DT/2
ns
tHHBGI
HBG Hold After CLKIN High
6 + DT/2
ns
tSBRI
BRx, CPA Setup Before CLKIN3
13 + DT/2
ns
tHBRI
BRx, CPA Hold After CLKIN High
6 + DT/2
ns
tSRPBAI
RPBA Setup Before CLKIN
21 + 3DT/4
ns
tHRPBAI
RPBA Hold After CLKIN
12 + 3DT/4
ns
Switching Characteristics
tDHBGO
HBG Delay After CLKIN
7 – DT/8
ns
tHHBGO
HBG Hold After CLKIN
–2 – DT/8
ns
tDBRO
BRx Delay After CLKIN
7 – DT/8
ns
tHBRO
BRx Hold After CLKIN
–2 – DT/8
ns
tDCPAO
CPA Low Delay After CLKIN4
8 – DT/8
ns
tTRCPA
CPA Disable After CLKIN
–2 – DT/8
4.5 – DT/8
ns
tDRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low5, 6
8.5
ns
tTRDYHG
REDY (O/D) Disable or REDY (A/D) High from HBG6, 7
44 + 23DT/16
ns
tARDYTR
REDY (A/D) Disable from CS or HBR High6
10
ns
1 For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes low. This is
easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC
User’s Manual, Revision 2.1.
2 Only required for recognition in the current cycle.
3 CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4 For ADSP-21060LC, specification is 8.5 – DT/8 ns max.
5 For ADSP-21060L, specification is 9.5 ns max, For ADSP-21060LC, specification is 11.0 ns max, For ADSP-21062L, specification is 8.75 ns max.
6 (O/D) = open drain, (A/D) = active drive.
7 For ADSP-21060C/ADSP-21060LC, specification is 40 + 23DT/16 ns min.
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