参数资料
型号: ADSP-21060LCB-133
厂商: Analog Devices Inc
文件页数: 37/64页
文件大小: 0K
描述: IC DSP CONTROLLER 32BIT 225BGA
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: 主机接口,连接端口,串行端口
时钟速率: 33MHz
非易失内存: 外部
芯片上RAM: 512kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 225-BBGA
供应商设备封装: 225-PBGA
包装: 托盘
Rev. F
|
Page 42 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Serial Ports
For serial ports, see Table 28, Table 29, Table 30, Table 31,
mine whether communication is possible between two devices
at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay
and data setup and hold, and 3) SCLK width.
Table 28. Serial Ports—External Clock
Parameter
5 V and 3.3 V
Min
Max
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
3.5
ns
tHFSE
TFS/RFS Hold After TCLK/RCLK1, 2
4ns
tSDRE
Receive Data Setup Before RCLK1
1.5
ns
tHDRE
Receive Data Hold After RCLK1
6.5
ns
tSCLKW
TCLK/RCLK Width3
9ns
tSCLK
TCLK/RCLK Period
2tCLK
ns
1 Referenced to sample edge.
2 RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3 For ADSP-21060/ADSP-21060C/ADSP-21060LC, specification is 9.5 ns min.
Table 29. Serial Ports—Internal Clock
Parameter
5 V and 3.3 V
Min
Max
Unit
Timing Requirements
tSFSI
TFS Setup Before TCLK1; RFS Setup Before RCLK1
8ns
tHFSI
TFS/RFS Hold After TCLK/RCLK1, 2
1ns
tSDRI
Receive Data Setup Before RCLK1
3ns
tHDRI
Receive Data Hold After RCLK1
3ns
1 Referenced to sample edge.
2 RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 30. Serial Ports—External or Internal Clock
Parameter
5 V and 3.3 V
Min
Max
Unit
Switching Characteristics
tDFSE
RFS Delay After RCLK (Internally Generated RFS)1
13
ns
tHOFSE
RFS Hold After RCLK (Internally Generated RFS)1
3ns
1 Referenced to drive edge.
Table 31. Serial Ports—External Clock
Parameter
5 V and 3.3 V
Min
Max
Unit
Switching Characteristics
tDFSE
TFS Delay After TCLK (Internally Generated TFS)1
13
ns
tHOFSE
TFS Hold After TCLK (Internally Generated TFS)1
3ns
tDDTE
Transmit Data Delay After TCLK1
16
ns
tHDTE
Transmit Data Hold After TCLK1
5ns
1 Referenced to drive edge.
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