参数资料
型号: ADSP-21160NKB-100
厂商: Analog Devices Inc
文件页数: 1/48页
文件大小: 0K
描述: IC DSP CONTROLLER 32BIT 400BGA
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: 主机接口,连接端口,串行端口
时钟速率: 100MHz
非易失内存: 外部
芯片上RAM: 512kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.90V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 400-BBGA
供应商设备封装: 400-PBGA(27x27)
包装: 托盘
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
REV. 0
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
a
S
DSP Microcomputer
ADSP-21160N
SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Graphics, Imaging, and
Communication
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Backwards Compatible—Assembly Source Level
Compatible with Code for ADSP-2106x DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Integrated Peripherals—Integrated I/O Processor,
4 M Bits On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping and Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
FUNCTIONAL BLOCK DIAGRAM
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16
40-BIT
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEX)
16
40-BIT
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
60
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
I/O PROCESSOR
DMA
CONTROLLER
TIMER
INSTRUCTION
CACHE
32
48-BIT
ADDR
DATA
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
DUAL-PORTED SRAM
JTAG
TEST AND
EMULATION
6
HOST PORT
ADDR BUS
MUX
IOA
18
IOD
64
MULTIPROCESSOR
INTERFACE
EXTERNAL
PORT
DATA BUS
MUX
64
32
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DAG1
8
4
32
16/32/40/48/64
32/40/64
CORE PROCESSOR
PROGRAM
SEQUENCER
DAG2
8
4
32
B
L
O
C
K
0
B
L
O
C
K
1
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
2003 Analog Devices, Inc. All rights reserved.
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