- 您现在的位置：买卖IC网 > PDF目录19372 > ADSP-21160NKB-100 (Analog Devices Inc)IC DSP CONTROLLER 32BIT 400BGA PDF资料下载
参数资料
| 型号： | ADSP-21160NKB-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 45/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400BGA |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 100MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.90V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-BBGA |
| 供应商设备封装： | 400-PBGA（27x27） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页当前第45页第46页第47页第48页
ADSP-21160N
–6–
REV. 0
PM data, DM addresses, DM data, I/O addresses, and I/O data—
are multiplexed at the external port to create an external system
bus with a single 32-bit address bus and a single 64-bit data bus.
The lower 32 bits of the external data bus connect to even
addresses and the upper 32 bits of the 64 connect to odd
addresses. Every access to external memory is based on an
address that fetches a 32-bit word, and with the 64-bit bus, two
address locations can be accessed at once. When fetching an
instruction from external memory, two 32-bit data locations are
being accessed (16 bits are unused). Figure 3 shows the
alignment of various accesses to external memory.
The external port supports asynchronous, synchronous, and syn-
chronous burst accesses. ZBT synchronous burst SRAM can be
interfaced gluelessly. Addressing of external memory devices is
facilitated by on-chip decoding of high order address lines to
generate memory bank select signals. Separate control lines are
also generated for simplified addressing of page-mode DRAM.
The ADSP-21160N provides programmable memory wait states
and external memory acknowledge controls to allow interfacing
to DRAM and peripherals with variable access, hold, and disable
time requirements.
DMA Controller
The ADSP-21160N’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions. DMA
transfers can occur between the ADSP-21160N’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP-
21160N’s internal memory and its serial ports or link ports.
External bus packing to 16-, 32-, 48-, or 64-bit words is
performed during DMA transfers. Fourteen channels of DMA
are available on the ADSP-21160N—six via the link ports, four
via the serial ports, and four via the processor’s external port (for
either host processor, other ADSP-21160Ns, memory or I/O
transfers). Programs can be downloaded to the ADSP-21160N
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(
DMAR1–2, DMAG1–2). Other DMA features include
interrupt generation upon completion of DMA transfers, two-
dimensional DMA, and DMA chaining for automatic linked
DMA transfers.
Multiprocessing
The ADSP-21160N offers powerful features tailored to multi-
processing DSP systems as shown in Figure 4. The external port
and link ports provide integrated glueless multiprocessing
support.
The external port supports a unified address space (see Figure 2)
that allows direct interprocessor accesses of each ADSP-
21160N’s internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems con-
taining up to six ADSP-21160Ns and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus
lock allows indivisible read-modify-write sequences for sema-
phores. A vector interrupt is provided for interprocessor
Figure 2. Memory Map
0x00 0000
0x02 0000
0x04 0000
0x08 0000
0x10 0000
0x20 0000
0x30 0000
0x40 0000
0x50 0000
0x60 0000
0x70 0000
0x7F FFFF
0x80 0000
0xFFFF FFFF
Internal
Memory
Space
External
Memory
Space
IOP Reg’s
Long Word
Normal Word
Short Word
Internal
Space
Internal
Space
Internal
Space
Internal
Space
Internal
Space
Internal
Space
Broadcast
All DSPs
Bank 0
Bank 1
Bank 2
Bank 3
Nonbanked
MS0
MS1
MS2
MS3
Memory
(ID = 011)
(ID = 100)
Memory
(ID = 101)
Memory
(ID = 110)
Write to
(ID = 111)
Memory
(ID = 010)
Memory
(ID = 001)
Multiprocessor
Memory
Space
Figure 3. External Data Alignment Options
DATA63–0
63
55
47
39
31
23
15
7
0
RDH/WRH
RDL/WRL
EPROM
16-BIT PACKED
32-BIT PACKED
64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION
64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH
RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:
64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS
BYTE 0
BYTE 7
32-BIT NORMAL WORD (EVEN ADDRESS)
32-BIT NORMAL WORD (ODD ADDRESS)
相关PDF资料 |
PDF描述 |
|---|---|
| RMM43DREH | CONN EDGECARD 86POS .156 EYELET |
| RS-0509D/H3 | CONV DC/DC 2W 4.5-9VIN +/-09V |
| GEM06DRUI | CONN EDGECARD 12POS DIP .156 SLD |
| EMM43DRMT | CONN EDGECARD 86POS .156 WW |
| MAX6639ATE+T | IC TEMP MONITOR 2CH 16-TQFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21160NKB-95 | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NKB-X | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21161N | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21161NCCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
发布紧急采购，3分钟左右您将得到回复。