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参数资料
| 型号： | ADSP-21478BCPZ-1A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/76页 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARK 200MHZ 88LFCSP |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 200MHz |
| 非易失内存： | ROM（4Mb） |
| 芯片上RAM： | 3Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 88-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 88-LFCSP-VQ（12x12） |
| 包装： | 托盘 |
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Rev. C
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Page 10 of 76
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July 2013
occupy a 8M word window in the processor’s address space but,
if not fully populated, these windows are not made contiguous
by the memory controller logic.
External Port Throughput
The throughput for the external port, based on 133 MHz clock
and 16-bit data bus, is 88 Mbytes/sec for the AMI and
266 Mbytes/sec for SDRAM.
MediaLB
The automotive models of the processors have an MLB interface
which allows the processor to function as a media local bus
device. It includes support for both 3-pin and 5-pin MLB proto-
cols. It supports speeds up to 1024 FS (49.25M bits/sec,
FS = 48.1 kHz) and up to 31 logical channels, with up to
124 bytes of data per media local bus frame. For a list of auto-
motive products, see Automotive Products on Page 75.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DAI pins
(DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with non con-
figurable signal paths.
The associated peripherals include eight serial ports, four preci-
sion clock generators (PCG), a S/PDIF transceiver, four ASRCs,
and an input data port (IDP). The IDP provides an additional
input path to the SHARC core, configurable as either eight
channels of serial data, or a single 20-bit wide synchronous par-
allel data acquisition port. Each data channel has its own DMA
channel that is independent from the processor’s serial ports.
Serial Ports (SPORTs)
The processors feature eight synchronous serial ports that pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial ports can support up to 16 transmit or 16 receive DMA
channels of audio data when all eight SPORTs are enabled, or
four full duplex TDM streams of 128 channels per frame.
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.
Serial ports operate in five modes:
Standard serial mode
Multichannel (TDM) mode
I2S mode
Packed I2S mode
Left-justified mode
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
bi phase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I2S or
right-justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources, such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
Asynchronous Sample Rate Converter (SRC)
The sample rate converter contains four blocks and is the same
core as that used in the AD1896 192 kHz stereo asynchronous
sample rate converter. The SRC block provides up to 128 dB
SNR and is used to perform synchronous or asynchronous sam-
ple rate conversion across independent stereo channels, without
using internal processor resources. The four SRC blocks can
also be configured to operate together to convert multichannel
audio data without phase mismatches. Finally, the SRC can be
used to clean up audio data from jittery clock sources such as
the S/PDIF receiver.
Input Data Port
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I2S, left-justified sample pair, or right-justified
mode.
The IDP also provides a parallel data acquisition port (PDAP)
which can be used for receiving parallel data. The PDAP port
has a clock input and a hold input. The data for the PDAP can
be received from DAI pins or from the external port pins. The
PDAP supports a maximum of 20-bit data and four different
packing modes to receive the incoming data.
Precision Clock Generators
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
The outputs of PCG A and B can be routed through the DAI
pins and the outputs of PCG C and D can be driven on to the
DAI as well as the DPI pins.
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