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参数资料
| 型号： | ADSP-21479KSWZ-2A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 45/72页 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARC 266MHZ LP 100LQFP |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 266MHz |
| 非易失内存： | ROM（4Mb） |
| 芯片上RAM： | 5Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP 裸露焊盘 |
| 供应商设备封装： | 100-LQFP-EP（14x14） |
| 包装： | 托盘 |
| 其它名称： | Q6418433 |
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Rev. A
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Page 5 of 72
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September 2011
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The processor’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs of the processors contain sufficient
registers to allow the creation of up to 32 circular buffers (16
primary register sets, 16 secondary). The DAGs automatically
handle address pointer wraparound, reduce overhead, increase
performance, and simplify implementation. Circular buffers can
start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
processors can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the processors support new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
SDRAM memory. This support is not extended to the asynchro-
nous memory interface (AMI). Source modules need to be built
using the VISA option, in order to allow code generation tools
to create these more efficient opcodes.
On-Chip Memory
The ADSP-21478 processor contains 3 Mbits of internal RAM
(Table 3) and the ADSP-21479 processor contains 5 Mbits of
internal RAM (Table 4). Each block can be configured for dif-
ferent combinations of code and data storage. Each memory
block supports single-cycle, independent accesses by the core
processor and I/O processor.
Figure 2. SHARC Core Block Diagram
S
SIMD Core
CACHE
INTERRUPT
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 32
DM ADDRESS 32
DM DATA 64
PM DATA 64
DAG1
16×32
MRF
80-BIT
ALU
MULTIPLIER
SHIFTER
RF
Rx/Fx
PEx
16×40-BIT
JTAG
DMD/PMD 64
ASTATx
STYKx
ASTATy
STYKy
TIMER
RF
Sx/SFx
PEy
16×40-BIT
MRB
80-BIT
MSB
80-BIT
MSF
80-BIT
FLAG
SYSTEM
I/F
USTAT
4×32-BIT
PX
64-BIT
DAG2
16×32
ALU
MULTIPLIER
SHIFTER
DATA
SWAP
PM ADDRESS 24
PM DATA 48
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21479SBC2-EP | 功能描述:IC DSP SHARC 266MHZ LP 制造商:analog devices inc. 系列:SHARC? 包装:托盘 零件状态:在售 类型:浮点 接口:DAI，DPI，EBI/EMI，I2C，SPI，SPORT，UART/USART 时钟速率:266MHz 非易失性存储器:ROM（4Mb） 片载 RAM:5Mb 电压 - I/O:3.30V 电压 - 内核:1.20V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:196-LFBGA，CSPBGA 供应商器件封装:196-CSPBGA（12x12） 标准包装:1 |
| ADSP-21483KSWZ-2B | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21483KSWZ-3AB | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21483KSWZ-3B | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21483KSWZ-4B | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
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