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| 型号： | ADSP-21479KSWZ-2A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 53/72页 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARC 266MHZ LP 100LQFP |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 266MHz |
| 非易失内存： | ROM（4Mb） |
| 芯片上RAM： | 5Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP 裸露焊盘 |
| 供应商设备封装： | 100-LQFP-EP（14x14） |
| 包装： | 托盘 |
| 其它名称： | Q6418433 |
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Rev. A
|
Page 57 of 72
|
September 2011
Shift Register
Table 53. Shift Register
Parameter
Min
Max
Unit
Timing Requirements
tSSDI
SR_SDI Setup Before SR_SCLK Rising Edge
7
ns
tHSDI
SR_SDI Hold After SR_SCLK Rising Edge
2
ns
tSSDIDAI
1
DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge
7
ns
tHSDIDAI
DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge
2
ns
tSSCK2LCK
2
SR_SCLK to SR_LAT Setup
2
ns
tSSCK2LCKDAI
DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup
2
ns
tCLRREM2SCK
Removal Time SR_CLR to SR_SDCLK
3 × tPCLK – 5
ns
tCLRREM2LCK
Removal Time SR_CLR to SR_LAT
2 × tPCLK – 5
ns
tCLRW
SR_CLR Pulse Width
4 × tPCLK – 5
ns
tSCKW
SR_SDCLK Clock Pulse Width
2 × tPCLK – 2
ns
tLCKW
SR_LAT Clock Pulse Width
2 × tPCLK – 5
ns
fMAX
Maximum Clock Frequency SR_SDCLK or SR_LAT
fCCLK
÷ 8MHz
Switching Characteristics
ns
tDSDO1
3
SR_SDO Hold After SR_SCLK Rising Edge
3
ns
tDSDO2
SR_SDO Max. Delay After SR_SCLK Rising Edge
13
ns
tDSDODAI1
SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge
3
ns
tDSDODAI2
SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge
13
ns
tDSDOSP1
3, 4
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
–2
ns
tDSDOSP2
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
5
ns
tDSDOPCG1
3, 5, 6
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
–2
ns
tDSDOPCG2
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
5
ns
tDSDOCLR1
SR_CLR to SR_SDO Min. Delay
4
ns
tDSDOCLR2
SR_CLR to SR_SDO Max. Delay
13
ns
tDLDO1
SR_LDO Hold After SR_LAT Rising Edge
3
ns
tDLDO2
SR_LDO Max. Delay After SR_LAT Rising Edge
13
ns
tDLDODAI1
SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge
3
ns
tDLDODAI2
SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge
13
ns
tDLDOSP1
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
–2
ns
tDLDOSP2
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
5
ns
tDLDOPCG1
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
–2
ns
tDLDOPCG2
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
5
ns
tDLDOCLR1
SR_CLR to SR_LDO Min. Delay
4
ns
tDLDOCLR2
SR_CLR to SR_LDO Max. Delay
14
ns
1 Any of the DAI_P08-01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU.
2 Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of
latch register data.
3 For setup/hold timing requirements of off-chip shift register interfacing devices.
4 SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01.
5 PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally.
6 PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.
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相关代理商/技术参数 |
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|---|---|
| ADSP-21479SBC2-EP | 功能描述:IC DSP SHARC 266MHZ LP 制造商:analog devices inc. 系列:SHARC? 包装:托盘 零件状态:在售 类型:浮点 接口:DAI，DPI，EBI/EMI，I2C，SPI，SPORT，UART/USART 时钟速率:266MHz 非易失性存储器:ROM（4Mb） 片载 RAM:5Mb 电压 - I/O:3.30V 电压 - 内核:1.20V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:196-LFBGA，CSPBGA 供应商器件封装:196-CSPBGA（12x12） 标准包装:1 |
| ADSP-21483KSWZ-2B | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21483KSWZ-3AB | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21483KSWZ-3B | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21483KSWZ-4B | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
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