参数资料
型号: ADSP-21991BBCZ
厂商: Analog Devices Inc
文件页数: 29/44页
文件大小: 0K
描述: IC DSP CTLR 16BIT 196CSPBGA
标准包装: 1
系列: ADSP-21xx
类型: 定点
接口: SPI,SSP
时钟速率: 150MHz
非易失内存: 外部
芯片上RAM: 112kB
电压 - 输入/输出: 3.30V
电压 - 核心: 2.50V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 196-BGA
供应商设备封装: 196-MBGA(15x15)
包装: 托盘
–35–
REV. 0
ADSP-21991
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Number of output pins that switch during each cycle (O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (VDD)
and is calculated by the formula below.
The load capacitance includes the package capacitance (CIN of
the processor). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2tCK). The write strobe can switch
every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK),
but selects can switch on each cycle. For example, estimate PEXT
with the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
One 64K 16 RAM chip is used with a load of 10 pF
Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
External data memory writes occur every other cycle, a
rate of 1/(4tHCLK), with 50% of the pins switching
The bus cycle time is 80 MHz (tHCLK = 12.5 ns)
The PEXT equation is calculated for each class of pins that can
drive as shown in Table 15.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
Where:
PEXT is from Table 15
PINT is IDDINT
2.5 V, using the calculation IDDINT listed
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
following equation.
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 18. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays
V from the measured output high or
output low voltage. The tDECAY is calculated with test loads CL and
IL, and with
V equal to 0.5 V.
P
EXT
OC
×
V
DD
2
×
f
×
=
Table 15. PEXT Calculation Example
Pin Type
No. of Pins
% Switching
C
f
VDD
2
= PEXT
Address
15
50
10 pF
20 MHz
10.9 V
= 0.01635 W
MSx
1
0
10 pF
20 MHz
10.9 V
= 0.0 W
WR
1
10 pF
40 MHz
10.9 V
= 0.00436 W
Data
16
50
10 pF
20 MHz
10.9 V
= 0.01744 W
CLKOUT
1
10 pF
80 MHz
10.9 V
= 0.00872 W
= 0.04687 W
P
TOTAL
P
=
EXT
P
INT
+
Figure 18. Output Enable/Disable
t
DECAY
C
L V
I
L
---------------
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V2.0V
VOL (MEASURED) + V1.0V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tDECAY
tENA
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