参数资料
型号: ADSP-21991BBCZ
厂商: Analog Devices Inc
文件页数: 30/44页
文件大小: 0K
描述: IC DSP CTLR 16BIT 196CSPBGA
标准包装: 1
系列: ADSP-21xx
类型: 定点
接口: SPI,SSP
时钟速率: 150MHz
非易失内存: 外部
芯片上RAM: 112kB
电压 - 输入/输出: 3.30V
电压 - 核心: 2.50V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 196-BGA
供应商设备封装: 196-MBGA(15x15)
包装: 托盘
ADSP-21991
–36–
REV. 0
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 18). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation at Output Disable Time
V to be the difference between the output
voltage of the ADSP-21991 and the input threshold for the device
requiring the hold time. A typical
V will be 0.4 V. CLis the total
bus capacitance (per data line), and IL is the total leakage or three-
state current (per data line). The hold time will be tDECAY plus the
minimum disable time (i.e., tDATRWH for the write cycle).
Pin Configurations
Table 16 identifies the signal for each Mini-BGA ball number.
Table 17 identifies the Mini-BGA ball number for each signal
name.
Table 18 identifies the signal for each LQFP lead.
Table 19 identifies the LQFP lead for each signal name.
Table 4 describes each signal.
Figure 19. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 20. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
INPUT
OR
OUTPUT
1.5V
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