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| 型号： | ADSP-21992BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/60页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 176LQFP |
| 标准包装： | 1 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | SPI，SSP |
| 时钟速率： | 160MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 2.50V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 176-LQFP |
| 供应商设备封装： | 176-LQFP（24x24） |
| 包装： | 托盘 |
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ADSP-21992
Rev. A
|
Page 51 of 60
|
August 2007
TEST CONDITIONS
The DSP is tested for output enable, disable, and hold time.
OUTPUT DISABLE TIME
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by the
following equation.
The output disable time tDIS is the difference between
SURED is the interval from when the reference signal switches to
when the output voltage decays ΔV from the measured output
high or output low voltage. The tDECAY is calculated with test
loads CL and IL, and with ΔV equal to 0.5 V.
OUTPUT ENABLE TIME
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 19). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
EXAMPLE SYSTEM HOLD TIME CALCULATION
To determine the data output hold time in a particular system,
on Page 51. Choose ΔV to be the difference between the output
voltage of the ADSP-21992 and the input threshold for the
device requiring the hold time. A typical ΔV will be 0.4 V. CL is
the total bus capacitance (per data line), and IL is the total leak-
age or three-state current (per data line). The hold time will be
tDECAY plus the minimum disable time (i.e., tDATRWH for the
write cycle).
Figure 19. Output Enable/Disable
Figure 20. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
tDECAY
CL V
Δ
IL
--------------
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V2.0V
VOL (MEASURED) + V1.0V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tDECAY
tENA
1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
Figure 21. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
INPUT
OR
OUTPUT
1.5V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21992YBC | 功能描述:IC DSP CTLR 16BIT 196CSPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:ADSP-21xx 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21992YST | 制造商:Analog Devices 功能描述: |
| ADSP-21BT101JST | 制造商:Analog Devices 功能描述: |
| ADSP21CSP01BS200 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP21CSP01KS200 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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