参数资料
型号: ADSP-BF531SBB400
厂商: Analog Devices Inc
文件页数: 32/64页
文件大小: 0K
描述: IC DSP CTLR 16BIT 400MHZ 169-BGA
产品培训模块: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1
系列: Blackfin®
类型: 定点
接口: SPI,SSP,UART
时钟速率: 400MHz
非易失内存: ROM(1 kB)
芯片上RAM: 52kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 169-BBGA
供应商设备封装: 169-PBGA(19x19)
包装: 托盘
配用: ADZS-BF533-EZLITE-ND - KIT W/BOARD EVAL FOR ADSP-BF533
ADSP-BF531 / ADSP-BF532 / ADSP-BF533
Parallel Peripheral Interface Timing
Table 27 and Figure 17 through Figure 22 describe parallel
peripheral interface operations.
Table 27. Parallel Peripheral Interface Timing
V DDEXT = 1.8 V
LQFP/PBGA Packages
V DDEXT = 1.8 V
CSP_BGA Package
V DDEXT = 2.5 V/3.3 V
All Packages
Parameter
Timing Requirements
Min Max
Min Max Min Max Unit
t PCLKW PPI_CLK Width
8.0
8.0
6.0
ns
t PCLK
t SFSPE
PPI_CLK Period 1
External Frame Sync Setup Before PPI_CLK Edge
20.0
6.0
20.0
6.0
15.0
4.0 2
ns
ns
(Nonsampling Edge for Rx, Sampling Edge for Tx)
ns
t HFSPE
t SDRPE
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
1.0 2
3.5
1.0 2
3.5
1.0 2
3.5
ns
ns
t HDRPE Receive Data Hold After PPI_CLK
1.5
1.5
1.5
ns
Switching Characteristics—GP Output and Frame Capture Modes
t DFSPE
Internal Frame Sync Delay After PPI_CLK
11.0
8.0
8.0
ns
t HOFSPE Internal Frame Sync Hold After PPI_CLK
t DDTPE Transmit Data Delay After PPI_CLK
t HDTPE Transmit Data Hold After PPI_CLK
1.7
1.8
11.0
1.7
1.8
9.0
1.7
1.8
9.0
ns
ns
ns
1
2
PPI_CLK frequency cannot exceed f SCLK /2.
Applies when PPI_CONTROL Bit 8 is cleared. See Figure 19 and Figure 22 .
PPI_CLK
FRAME SYNC
DRIVEN
DATA
SAMPLED
t HOFSPE
t DFSPE
t PCLKW
t PCLK
PPI_FS1/2
t SDRPE
t HDRPE
PPI_DATA
Figure 17. PPI GP Rx Mode with Internal Frame Sync Timing
PPI_CLK
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
t SFSPE
t HFSPE
t PCLKW
t PCLK
PPI_FS1/2
t SDRPE
t HDRPE
PPI_DATA
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
Rev. I
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Page 32 of 64 |
August 2013
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