参数资料
型号: ADSP-BF531SBBCZ4RL
厂商: Analog Devices Inc
文件页数: 42/64页
文件大小: 0K
描述: IC DSP CTLR 16BIT 400MHZ 160-CSP
产品培训模块: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
标准包装: 1
系列: Blackfin®
类型: 定点
接口: SPI,SSP,UART
时钟速率: 400MHz
非易失内存: ROM(1 kB)
芯片上RAM: 52kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 160-LFBGA,CSPBGA
供应商设备封装: 160-CSPBGA(12x12)
包装: 标准包装
其它名称: ADSP-BF531SBBCZ4RLDKR
ADSP-BF531 / ADSP-BF532 / ADSP-BF533
JTAG Test and Emulation Port Timing
Table 37. JTAG Port Timing
V DDEXT = 1.8 V
V DDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min Max
Unit
Timing Requirements
t TCK
t STAP
t HTAP
t SSYS
t HSYS
t TRSTW
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High 1
System Inputs Hold After TCK High 1
TRST Pulse Width 2 (Measured in TCK Cycles)
20
4
4
4
5
4
20
4
4
4
5
4
ns
ns
ns
ns
ns
TCK
Switching Characteristics
t DTDO
TDO Delay from TCK Low
10
10
ns
t DSYS
System Outputs Delay After TCK Low 3
0
12
0
12
ns
1
2
3
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PPI3–0.
50 MHz maximum.
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
t TCK
TCK
TMS
TDI
TDO
t DTDO
t STAP
t SSYS
t HTAP
t HSYS
SYSTEM
INPUTS
t DSYS
SYSTEM
OUTPUTS
Figure 32. JTAG Port Timing
Rev. I
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Page 42 of 64 |
August 2013
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