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参数资料
| 型号： | ADSP-BF533SBBC500 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16B 500MHZ 160CSPBGA |
| 产品培训模块： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | SPI，SSP，UART |
| 时钟速率： | 500MHz |
| 非易失内存： | ROM（1 kB） |
| 芯片上RAM： | 148kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 160-LFBGA，CSPBGA |
| 供应商设备封装： | 160-CSPBGA（12x12） |
| 包装： | 托盘 |
| 配用： | ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT ADZS-BF533-EZLITE-ND - KIT W/BOARD EVAL FOR ADSP-BF533 |
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ADSP-BF531 / ADSP-BF532 / ADSP-BF533
t NOM is the duration running at f CCLKNOM
t RED is the duration running at f CCLKRED
The percent power savings is calculated as:
% power savings = ? 1 – power savings factor ? ? 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate appropriate V DDINT voltage levels from the
V DDEXT supply. See Operating Conditions on Page 20 for regula-
tor tolerances and acceptable V DDEXT ranges for specific models.
complete the power management system. The regulator con-
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power (V DDEXT ) supplied.
While in the hibernate state, I/O power is still being applied,
eliminating the need for external buffers. The voltage regulator
can be activated from this power-down state either through an
For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
log.com )—use site search on “EE-228”.
CLOCK SIGNALS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors can
be clocked by an external crystal, a sine wave input, or a buff-
ered, shaped clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processors include an on-chip oscilla-
tor circuit, an external crystal can be used. For fundamental
Blackfin
RTC wakeup or by asserting RESET, both of which initiate a
boot sequence. The regulator can also be disabled and bypassed
at the user’s discretion.
CLKOUT
EN
TO PLL CIRCUITRY
V DDEXT
(LOW-INDUCTANCE)
SET OF DECOUPLING
CAPACITORS
700
100μF
+
V DDEXT
CLKIN
XTAL
0 *
V DDEXT
1M
100nF
10μH
100μF
+
FDS9431A
+
V DDINT
18pF*
18pF*
FOR OVERTONE
OPERATION ONLY
10μF
100μF
LOW ESR
ZHCS1000
VR OUT
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
SHORT AND LOW-
INDUCTANCE WIRE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
Figure 7. Voltage Regulator Circuit
VR OUT
GND
Figure 8. External Crystal Connections
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 k ? range. Further parallel resistors are typically not rec-
ommended. The two capacitors and the series resistor shown in
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1–0 traces
and voltage regulator external components should be consid-
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the proces-
sors as possible.
quency. The capacitor and resistor values shown in Figure 8 are
typical values only. The capacitor values are dependent upon
the crystal manufacturer's load capacitance recommendations
and the physical PCB layout. The resistor value depends on the
drive level specified by the crystal manufacturer. System designs
should verify the customized values based on careful investiga-
tion on multiple devices over the allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
Rev. I
|
Page 13 of 64 |
August 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSPBF533SBBC-500 | 制造商:Analog Devices 功能描述:Dual MAC16-bit500MHz 148KB SRAM |
| ADSPBF533SBBC500X | 制造商:Analog Devices 功能描述: |
| ADSP-BF533SBBC-500X | 制造商:Analog Devices 功能描述: |
| ADSP-BF533SBBC-5V | 功能描述:IC DSP CTLR DUAL 160CSPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-BF533SBBC-C10 | 制造商:Analog Devices 功能描述: |
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