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参数资料
| 型号： | ADSP-BF561SKBCZ-5A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 32BIT BKFN 256CSPBGA |
| 产品培训模块： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | SPI，SSP，UART |
| 时钟速率： | 533MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 328kB |
| 电压 - 输入/输出： | 2.50V，3.30V |
| 电压 - 核心： | 1.25V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 配用： | ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN ADZS-BF561-EZLITE-ND - BOARD EVAL ADSP-BF561 ADZS-BF561-MMSKIT-ND - KIT STARTER MULTIMEDIA BF561 ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT |
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ADSP-BF561
? All registers, I/O, and memory are mapped into a unified
4G byte memory space providing a simplified program-
ming model.
? Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and ker-
nel stack pointers.
? Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded as
16-bits.
DEVELOPMENT TOOLS
The ADSP-BF561 is supported with a complete set of
CROSSCORE ? ? software and hardware development tools,
including Analog Devices emulators and the VisualDSP++ ? ?
development environment. The same emulator hardware that
supports other Analog Devices processors also fully emulates
the ADSP-BF561.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler that is based on an algebraic
syntax, an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathemati-
cal functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient trans-
lation of C/C++ code to Blackfin assembly. The Blackfin
processor has architectural features that improve the efficiency
of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
? View mixed C/C++ and assembly code (interleaved source
and object information).
? Insert breakpoints.
? Set conditional breakpoints on registers, memory, and
stacks.
? Trace instruction execution.
? Perform linear or statistical profiling of program execution.
? Fill, dump, and graphically plot the contents of memory.
? Perform source level debugging.
? Create custom debugger windows.
The VisualDSP++ IDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all development tools,
including color syntax highlighting in the VisualDSP++ editor.
These capabilities permit programmers to:
? Control how the development tools process inputs and
generate outputs.
? Maintain a one-to-one correspondence with the tool’s
command line switches.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of embedded, real-time
programming. These capabilities enable engineers to develop
code more effectively, eliminating the need to start from the
very beginning when developing new application code. The
VDK features include threads, critical and unscheduled regions,
semaphores, events, and device flags. The VDK also supports
priority-based, pre-emptive, cooperative, and time-sliced
scheduling approaches. In addition, the VDK was designed to
be scalable. If the application does not use a specific feature, the
support code for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used with standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the
generation of various VDK-based objects, and visualizing the
system state when debugging an application that uses the VDK.
The Expert Linker can be used to visually manipulate the place-
ment of code and data in the embedded system. Memory
utilization can be viewed in a color-coded graphical form. Code
and data can be easily moved to different areas of the processor
or external memory with the drag of the mouse. Runtime stack
and heap usage can be examined. The Expert Linker is fully
compatible with existing Linker Definition File (LDF), allowing
the developer to move between the graphical and textual
environments.
Analog Devices emulators use the IEEE 1149.1 JTAG test access
port of the ADSP-BF561 to monitor and control the target
board processor during emulation. The emulator provides full-
speed emulation, allowing inspection and modification of mem-
ory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect the loading or timing of the
?
?
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
target system.
Rev. E |
Page 15 of 64 |
September 2009
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| ADSP-BF561SKBCZ-5V | 功能描述:IC DSP 32BIT 500MHZ 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-BF561SKBCZ600 | 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 600MHZ 600MIPS 256CSPBGA - Trays 制造商:Analog Devices 功能描述:IC MULTI-PROCESSOR |
| ADSP-BF561SKBCZ-6A | 功能描述:IC DSP CTRLR 32B 600MHZ 256CPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF561SKBCZ-6A | 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
| ADSP-BF561SKBCZ-6V | 功能描述:IC DSP 32BIT 600MHZ 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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