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| 型号： | ADSP-BF561SKBCZ-6A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 43/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP CTRLR 32B 600MHZ 256CPBGA |
| 产品培训模块： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | SPI，SSP，UART |
| 时钟速率： | 600MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 328kB |
| 电压 - 输入/输出： | 2.50V，3.30V |
| 电压 - 核心： | 1.35V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 配用： | ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN ADZS-BF561-EZLITE-ND - BOARD EVAL ADSP-BF561 ADZS-BF561-MMSKIT-ND - KIT STARTER MULTIMEDIA BF561 ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT |
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ADSP-BF561
The time for the voltage on the bus to decay by Δ V is dependent
on the capacitive load C L and the load current I L . This decay time
can be approximated by the equation:
14
12
t DECAY = ( C L Δ V ) ? I L
The time t DECAY is calculated with test loads C L and I L , and with
Δ V equal to 0.5 V for V DDEXT (nominal) = 2.5 V/3.3 V.
The time t DIS _ MEASURED is the interval from when the reference sig-
nal switches, to when the output voltage decays Δ V from the
measured output high or output low voltage.
Example System Hold Time Calculation
10
8
6
4
2
RISE TIME
FALL TIME
To determine the data output hold time in a particular system,
first calculate t DECAY using the equation given above. Choose Δ V
0
0
50
100 150
LOAD CAPACITANCE (pF)
200
250
to be the difference between the ADSP-BF561 processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C L is the total bus capacitance (per data line), and I L is
the total leakage or three-state current (per data line). The hold
time will be t DECAY plus the various output disable times as speci-
fied in the Timing Specifications on Page 23 (for example t DSDAT
REFERENCE
Figure 40. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V DDEXT (min)
12
10
RISE TIME
8
FALL TIME
6
SIGNAL
4
t DIS_MEASURED
t ENA_MEASURED
t DIS
t ENA
2
V OH
(MEASURED)
V OL
(MEASURED)
V OH (MEASURED)
V OL (MEASURED) +
V
V
V OH (MEASURED)
V TRIP (HIGH)
V TRIP (LOW)
V OL (MEASURED)
0
0
50
100 150
LOAD CAPACITANCE (pF)
200
250
t DECAY
OUTPUT STOPS DRIVING
t TRIP
OUTPUT STARTS DRIVING
Figure 41. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V DDEXT (max)
12
HIGH IMPEDANCE STATE
Figure 38. Output Enable/Disable
Capacitive Loading
10
8
RISE TIME
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 39 ). V LOAD is 1.5 V for V DDEXT (nomi-
nal) = 2.5 V/3.3 V. Figure 40 through Figure 47 on Page 44 show
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
from these figures. The graphs in these figures may not be linear
outside the ranges shown.
6
4
2
FALL TIME
TO
OUTPUT
50 O
V LOAD
0
0
50
100 150
LOAD CAPACITANCE (pF)
200
250
PIN
30pF
Figure 39. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 42. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at V DDEXT (min)
Rev. E |
Page 43 of 64 |
September 2009
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF561SKBCZ-6A | 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
| ADSP-BF561SKBCZ-6V | 功能描述:IC DSP 32BIT 600MHZ 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-BF561SKBCZC70 | 制造商:Analog Devices 功能描述: |
| ADSPBF561SKBCZ-C70 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-BF561SKBCZENG | 制造商:Analog Devices 功能描述:- Trays |
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