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参数资料
| 型号： | ADUC7060BCPZ32-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 62/108页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 24BIT 32KB 48LFCSP |
| 设计资源： | 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164) |
| 标准包装： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | POR，PWM，温度传感器，WDT |
| 输入/输出数： | 14 |
| 程序存储器容量： | 32KB（16K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 数据转换器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
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Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 57 of 108
DAC0DAT Register
Name:
DAC0DAT
Address:
0xFFFF0604
Default value: 0x00000000
Access:
Read and write
Function:
This 32-bit MMR contains the DAC output
value.
Table 64. DAC0DAT MMR Bit Designations
Bit
Description
31:28
Reserved.
27:16
12-bit data for DAC0.
15:12
Extra four bits used in interpolation mode.
11:0
Reserved.
USING THE DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier.
The reference source for the DAC is user selectable in software. It
can be AVDD, VREF±, or ADCx/EXT_REF2IN±.
In 0-to-AVDD mode, the DAC output transfer function
spans from 0 V to the voltage at the AVDD pin.
In VREF± and ADCx/EXT_REF2IN± modes, the DAC
output transfer function spans from negative input voltage
to the voltage positive input pin. Note that these voltages
must never go below 0 V or above AVDD.
In 0-to-VREF mode, the DAC output transfer function spans
from 0 V to the internal 1.2 V reference, VREF.
The DAC can be configured in three different user modes:
normal mode, DAC interpolation mode, and op amp mode.
Normal DAC Mode
In this mode of operation, the DAC is configured as a 12-bit
voltage output DAC. By default, the DAC buffer is enabled, but
the output buffer can be disabled. If the DAC output buffer is
disabled, the DAC is capable of driving a capacitive load of only
20 pF. The DAC buffer is disabled by setting the DACBUFBYPASS
bit in DAC0CON.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AVDD and ground. Moreover, the linearity specification of
the DAC (when driving a 5 kΩ resistive load to ground) is guar-
anteed through the full transfer function except for Code 0
to Code 100 and, in 0-to- AVDD mode only, Code 3995 to
Code 4095. Linearity degradation near ground and AVDD is
caused by saturation of the output amplifier, and a general
representation of its effects (neglecting offset and gain error) is
illustrated in Figure 21. The dotted line in Figure 21 indicates the
ideal transfer function, and the solid line represents what the
transfer function may look like with endpoint nonlinearities due
to saturation of the output amplifier. Note that Figure 21 repre-
sents a transfer function in 0-to-AVDD mode only. In 0-to-VREF
or, VREF±, and ADCx/EXT_REF2IN± modes (with VREF < AVDD
or ADCx/EXT_REF2IN± < AVDD), the lower nonlinearity is
similar. However, the upper portion of the transfer function
follows the ideal line all the way to the end (VREF in this case, not
AVDD), showing no signs of endpoint linearity errors.
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
07079-
015
Figure 21. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 21
worsen as a function of output loading. Most of the ADuC706x
data sheet specifications in normal mode assume a 5 k
resistive load to ground at the DAC output. As the output is
forced to source or sink more current, the nonlinear regions at
the top or bottom (respectively) of Figure 21 become larger.
With larger current demands, this can significantly limit output
voltage swing.
DAC Interpolation Mode
In interpolation mode, a higher DAC output resolution of 16 bits
is achieved with a longer update rate than normal mode. The
update rate is controlled by the interpolation clock rate selected
in the DAC0CON register. In this mode, an external RC filter is
required to create a constant voltage.
Op Amp Mode
In op amp mode, the DAC output buffer is used as an op amp
with the DAC itself disabled.
ADC6 is the positive input to the op amp, ADC7 is the negative
input, and ADC8 is the output. In this mode, the DAC should
be powered down by setting Bit 9 of DAC0CON.
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