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| 型号： | ADUC814BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/72页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 28TSSOP |
| 标准包装： | 50 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，温度传感器，WDT |
| 输入/输出数： | 17 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 6x12b; D/A 2x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 28 of 72
ADCDATAH
ADCDATAL
ADCDATAH
ADCDATAL
ADCDATAH
ADCDATAL
MOSI
SCLOCK
BUSY
CONVST
02748-A
-037
Figure 30. High Speed Data Capture Logic Timing (Pipelined Mode)
In this mode, the ADC to SPI data transfer occurs during the
next ADC conversion. To avoid loss of an ADC result, the user
must ensure that the ADC to SPI transfer rate is complete
before the current ADC conversion ends.
To enable HSDC mode, Bit 6 in ADCCON2 (ADCSPI) must be
set and to enable the ADuC814 to capture a contiguous sample
stream at full ADC update rates (247 kHz).
To configure the ADuC814 in HSDC mode:
1.
The ADC must be put into one of its conversion modes.
2.
The SPI interface must be configured. (The SPI configura-
tion is detailed in the Serial Peripheral Interface section).
3.
Enable HSDC by setting the ADCSPI bit in the ADCCON2
SFR.
4.
Apply trigger signal to the ADC to perform conversions.
Once configured and enabled, the ADC results are transferred
from the ADCDATAH/L SFRs to the SPIDAT register. Figure 31
shows the HSDC logic configuration once the mode is enabled.
The ADC result is transmitted most significant bit first. In this
case, the channel ID is transmitted first, followed by the 12-bit
ADC result. When this mode is enabled, normal SPI and Port 3
operation is disabled; however, the core is free to continue code
execution, including general housekeeping and communication
tasks. This mode is disabled by clearing the ADCSPI bit.
MUX
SPIDAT
8
16
8
0
1
01
ADC TO SPI CONTROL LOGIC
A
DCDA
TA
H
A
DCDA
TA
L
R
E
GISTER
ADC
EDC
SPI LOGIC
DATA
REGISTER
END OF
CONVERSION
SIGNAL
02748-A
-068
Figure 31. High Speed Data Capture Logic
ADC OFFSET AND GAIN CALIBRATION OVERVIEW
The ADC block incorporates calibration hardware and
associated SFRs, which ensures optimum offset and gain
performance from the ADC at all times.
As part of internal factory final test routines, the ADuC814 is
calibrated to its offset and gain specifications. The offset and
gain coefficients obtained from this factory calibration are
stored in non-volatile Flash/EE memory. These are downloaded
from the Flash/EE memory to offset and gain calibration
registers automatically on a power-up or a reset event.
In many applications these factory-generated calibration
coefficients suffice. However, the ADuC814 ADC offset and
gain accuracy may vary from system to system due to board
layout, grounding, clock speed, or system configuration, and so
on. To get the best ADC accuracy in your system, an ADC
calibration should be performed.
Two main advantages are derived from ensuring the ADC
calibration registers are initialized correctly. First, the internal
errors in the ADC can be reduced significantly to give superior
dc performance; and second, system offset and gain errors can
be removed. This allows the user to remove reference errors
(whether an internal or external reference) and to use the full
dynamic range of the ADC by adjusting the analog input range
of the part for a specific system.
ADC OFFSET AND GAIN CALIBRATION
COEFFICIENTS
The ADuC814 has two ADC calibration coefficients, one for
offset calibration and one for gain calibration. Both the offset
and gain calibration coefficients are 14-bit words, and each is
stored in two registers located in the special function register
(SFR) area. The offset calibration coefficient is divided into
ADCOFSH (6 bits) and ADCOFSL (8 bits), and the gain cali-
bration coefficient is divided into ADCGAINH (6 bits) and
ADCGAINL (8 bits).
The offset calibration coefficient compensates for dc offset
errors in both the ADC and the input signal. Increasing the
offset coefficient compensates for positive offset, and effectively
pushes down the ADC transfer function. Decreasing the offset
coefficient compensates for negative offset, and effectively pushes
up the ADC transfer function. The maximum offset that can be
compensated is typically ± 3.5% of VREF, which equates to typi-
cally ±87.5 mV with a 2.5 V reference.
Similarly, the gain calibration coefficient compensates for dc
gain errors in both the ADC and the input signal. Increasing the
gain coefficient compensates for a smaller analog input signal
range and scales up the ADC transfer function, effectively
increasing the slope of the transfer function. Decreasing the
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