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| 型号： | ADUC814BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 71/72页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 28TSSOP |
| 标准包装： | 50 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，温度传感器，WDT |
| 输入/输出数： | 17 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 6x12b; D/A 2x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 8 of 72
1Temperature range –40C to +125C.
2ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also
guaranteed during normal MicroConverter core operation.
3ADC LSB size = VREF /212, i.e., for internal VREF = 2.5 V, 1 LSB = 610 V, and for external VREF = 1 V, 1 LSB = 244 V.
4Offset and gain error and offset and gain error match are measured after factory calibration.
5Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors
and achieve these specifications.
6Measured with coherent sampling system using external 16.77 MHz clock via P3.5 (Pin 22).
7SNR calculation includes distortion and noise components.
8Channel-to-channel crosstalk is measured on adjacent channels.
9The temperature monitor gives a measure of the die temperature directly; air temperature can be inferred from this result.
10DAC linearity is calculated using a reduced code range of 48 to 4095, 0 V to VREF range; a reduced code range of 48 to 3950, 0 V to VDD range. DAC output load = 10 k
and 100 pF.
11DAC differential nonlinearity specified on 0 V to VREF and 0 to VDD ranges.
12Measured with VREF and CREF pins decoupled with 0.1 F capacitors to ground. Power-up time for the internal reference is determined by the value of the decoupling
capacitor chosen for both the VREF and CREF pins.
13When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the VREF and CREF pins
need to be shorted together for correct operation.
14These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
15Pins configured in I2C compatible mode or SPI mode; pins configured as digital inputs during this test.
16These typical specifications assume no loading on the XTAL2 pin. Any additional loading on the XTAL2 pin increases the power-on times.
17Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
18Endurance is qualified to 100 kcycles as per JEDEC Std. 22, Method A117 and measured at –40C, +25°C, and +125°C; typical endurance at +25°C is 700 kcycles.
19Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature as shown in Figure 33 in the Flash/EE memory description section.
20Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions:
Normal Mode: Reset and all digital I/O pins = open circuit, core Clk changed via CD bits in PLLCON, core executing internal software loop.
Idle Mode: Reset and all digital I/O pins = open circuit, core Clk changed via CD bits in PLLCON, PCON.0 = 1, core execution suspended in idle mode.
Power-Down Mode: Reset and all P1.2–P1.7 pins = 0.4 V; all other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1,
Core execution suspended in power-down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR.
21DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
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