参数资料
型号: ADUC843BCPZ8-3
厂商: Analog Devices Inc
文件页数: 30/88页
文件大小: 0K
描述: IC MCU FLASH 12BIT ADC 56LFCSP
标准包装: 1
系列: MicroConverter® ADuC8xx
核心处理器: 8052
芯体尺寸: 8-位
速度: 8.38MHz
连通性: I²C,SPI,UART/USART
外围设备: DMA,PSM,PWM,温度传感器,WDT
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 56-VFQFN 裸露焊盘,CSP
包装: 托盘
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 36 of 88
ADuC842/ADuC843 Configuration SFR (CFG842)
The CFG842 SFR contains the necessary bits to configure the
internal XRAM, external clock select, PWM output selection,
DAC buffer, and the extended SP for both the ADuC842 and the
ADuC843. By default, it configures the user into 8051 mode, i.e.,
extended SP is disabled and internal XRAM is disabled. On the
ADuC841, this register is the CFG841 register and is described
on the next page.
CFG842
ADuC842/ADuC843 Config SFR
SFR Address
AFH
Power-On Default
00H
Bit Addressable
No
Table 13. CFG842 SFR Bit Designations
Bit No.
Name
Description
7
EXSP
Extended SP Enable.
When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H.
When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H.
6
PWPO
PWM Pin Out Selection.
Set to 1 by the user to select P3.4 and P3.3 as the PWM output pins.
Set to 0 by the user to select P2.6 and P2.7 as the PWM output pins.
5
DBUF
DAC Output Buffer.
Set to 1 by the user to bypass the DAC output buffer.
Set to 0 by the user to enable the DAC output buffer.
4
EXTCLK
Set by the user to 1 to select an external clock input on P3.4.
Set by the user to 0 to use the internal PLL clock.
3
RSVD
Reserved. This bit should always contain 0.
2
RSVD
Reserved. This bit should always contain 0.
1
MSPI
Set to 1 by the user to move the SPI functionality of MISO, MOSI, and SCLOCK to P3.3, P3.4, and P3.5,
respectively.
Set to 0 by the user to leave the SPI functionality as usual on MISO, MOSI, and SCLOCK pins.
0
XRAMEN
XRAM Enable Bit.
When set to 1 by the user, the internal XRAM is mapped into the lower 2 kBytes of the external address
space.
When set to 0 by the user, the internal XRAM is not accessible, and the external data memory is
mapped into the lower 2 kBytes of external data memory.
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