参数资料
型号: AGLE3000V2-FGG484I
厂商: Microsemi SoC
文件页数: 83/166页
文件大小: 0K
描述: IC FPGA 1KB FLASH 3M 484-FBGA
标准包装: 60
系列: IGLOOe
逻辑元件/单元数: 75264
RAM 位总计: 516096
输入/输出数: 341
门数: 3000000
电源电压: 1.14 V ~ 1.575 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
IGLOOe Low Power Flash FPGAs
Revision 13
2-9
Power per I/O Pin
Table 2-13 Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
VCCI
(V)
Static Power
PDC6 (mW)1
Dynamic Power
PAC9 (W/MHz)2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3
16.34
3.3 V LVTTL/LVCMOS – Schmitt trigger
3.3
24.49
3.3 V LVCMOS Wide Range 3
3.3
16.34
3.3 V LVCMOS Wide Range – Schmitt trigger 3
3.3
24.49
2.5 V LVCMOS
2.5
4.71
2.5 V LVCMOS
2.5
6.13
1.8 V LVCMOS
1.8
1.66
1.8 V LVCMOS – Schmitt trigger
1.8
1.78
1.5 V LVCMOS (JESD8-11)
1.5
1.01
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
1.5
0.97
1.2 V LVCMOS 4
1.2
0.60
1.2 V LVCMOS – Schmitt trigger 4
1.2
0.53
1.2 V LVCMOS Wide Range 4
1.2
0.60
1.2 V LVCMOS Wide Range – Schmitt trigger 4
1.2
0.53
3.3 V PCI
3.3
17.76
3.3 V PCI – Schmitt trigger
3.3
19.10
3.3 V PCI-X
3.3
17.76
3.3 V PCI-X – Schmitt trigger
3.3
19.10
Voltage-Referenced
3.3 V GTL
3.3
2.90
7.14
2.5 V GTL
2.5
2.13
3.54
3.3 V GTL+
3.3
2.81
2.91
2.5 V GTL+
2.5
2.57
2.61
HSTL (I)
1.5
0.17
0.79
HSTL (II)
1.5
0.17
.079
SSTL2 (I)
2.5
1.38
3.26
SSTL2 (II)
2.5
1.38
3.26
SSTL3 (I)
3.3
3.21
7.97
SSTL3 (II)
3.3
3.21
7.97
Differential
LVDS
2.5
2.26
0.89
LVPECL
3.3
5.71
1.94
Notes:
1. PDC6 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
4. Applicable for IGLOOe V2 devices only.
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