参数资料
型号: AGLE600V2-FFG256C
元件分类: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA256
封装: 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256
文件页数: 105/156页
文件大小: 5023K
代理商: AGLE600V2-FFG256C
IGLOOe DC and Switching Characteristics
2- 38
Advance v0.3
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-51 Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive
Strength Min., V
Max., V
Min., V
Max., V
Min., V
mA mA Max., mA1 Max., mA1 A2 A2
2 mA
–0.3
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2
2
13
16
10 10
4 mA
–0.3
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4
4
25
33
10 10
6 mA
–0.3
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6
6
32
39
10 10
8 mA
–0.3
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8
8
66
55
10 10
12 mA
–0.3
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
66
55
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Figure 2-10 AC Loading
Table 2-52 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point*
(V)
VREF (typ.) (V)
CLOAD (pF)
0
1.5
0.75
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
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