- 您现在的位置：买卖IC网 > PDF目录235794 > AGLE600V2-FFG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256 PDF资料下载
参数资料
| 型号： | AGLE600V2-FFG256C |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| 封装： | 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256 |
| 文件页数： | 124/156页 |
| 文件大小： | 5023K |
| 代理商： | AGLE600V2-FFG256C |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页当前第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页
IGLOOe Low-Power Flash FPGAs
v1.2
1 - 3
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, Flash-based IGLOOe devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property cannot be compromised or copied.
Secure ISP can be performed using the industry-standard AES algorithm. The IGLOOe family device
architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOOe
family a cost-effective ASIC replacement solution, especially for applications in the consumer,
networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,
strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.
These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be
a complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flash-
based FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot
be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error
detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through
an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS
design techniques are used to implement logic and control functions. The combination of fine
granularity, enhanced flexible routing resources, and abundant flash switches allows for very high
logic utilization without compromising device routability or performance. Logic functions within
the device are interconnected through a four-level routing hierarchy.
IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all
modes of operation.
Advanced Architecture
The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The
IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the IGLOOe core tile as either a three-input lookup
table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric.
The VersaTile capability is unique to the Actel ProASIC family of third-generation-architecture
flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash
switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect
programming. Maximum core utilization is possible for virtually any design.
相关PDF资料 |
PDF描述 |
|---|---|
| AGLE600V2-FFG484C | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
| AGLE600V2-FFGG256C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V2-FFGG484C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V2-FG256C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V2-FGG256C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AGLE600V2-FFG896 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V2-FFG896ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V2-FFG896I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V2-FFG896PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V2-FFGG896 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
发布紧急采购，3分钟左右您将得到回复。