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参数资料
| 型号： | AM29DL162DB90PCI |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA64 |
| 封装： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-64 |
| 文件页数： | 4/56页 |
| 文件大小： | 1752K |
| 代理商： | AM29DL162DB90PCI |
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12
Am29DL16xD
February 14, 2003
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dr es s a c ce ss ti mi ngs pr ov i de ne w dat a whe n
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
RP,
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS±0.3 V, the device
draws CMOS standby current (I
CC4). If RESET# is held
at V
IL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
READY (not during Embed-
ded Algorithms). The system can read data t
RH after
the RESET# pin returns to V
IH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2.
Am29DL16xD Device Bank Divisions
Device
Part Number
Bank 1
Bank 2
Megabits
Sector Sizes
Megabits
Sector Sizes
Am29DL161D
0.5 Mbit
Eight 8 Kbyte/4 Kword
15.5 Mbit
Thirty-one
64 Kbyte/32 Kword
Am29DL162D
2 Mbit
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
14 Mbit
Twenty-eight
64 Kbyte/32 Kword
Am29DL163D
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
12 Mbit
Twenty-four
64 Kbyte/32 Kword
Am29DL164D
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
8 Mbit
Sixteen
64 Kbyte/32 Kword
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