参数资料
型号: AM29F017D
厂商: Spansion Inc.
英文描述: 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
中文描述: 16兆位(2米× 8位)的CMOS 5.0伏只,统一部门快闪记忆体
文件页数: 3/44页
文件大小: 1021K
代理商: AM29F017D
10
Am29F017D
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re-
quires standard access time (tCE) for read access when
the device is in either of these standby modes, before it
is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, “RE-
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
相关PDF资料
PDF描述
AM29F017D-120 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AM29F032B-150SE 4M X 8 FLASH 5V PROM, 150 ns, PDSO44
AM29F032B-75FC 4M X 8 FLASH 5V PROM, 70 ns, PDSO40
AM29F080-120SEB 1M X 8 FLASH 5V PROM, 120 ns, PDSO44
AM29F080-150EEB 1M X 8 FLASH 5V PROM, 150 ns, PDSO40
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