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参数资料
| 型号： | Am29LV400B-90RWAEB |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | CAP 0.47UF 50V +50-20% X7R SMD-0612 TR-7 PLATED-NI/SN HC-FEEDTHRU |
| 中文描述： | 4兆位（512亩x 8-Bit/256亩x 16位），3.0伏的CMOS只引导扇区闪存 |
| 文件页数： | 12/40页 |
| 文件大小： | 516K |
| 代理商： | AM29LV400B-90RWAEB |
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Am29LV400
2
PREL I M I N AR Y
GENERAL DESCRIPTION
The Am29LV400 is a 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 48-ball FBGA, 44-pin SO, and
48-pin TSOP packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed in-system using only a single 3.0 volt VCC
supply. No VPP is required for write or erase opera-
tions. The device can also be programmed in standard
EPROM programmers.
The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
相关PDF资料 |
PDF描述 |
|---|---|
| Am29LV400BB70RWACB | Ceramic Multilayer Capacitor; Capacitance:470pF; Capacitance Tolerance:+50, -20 %; Working Voltage, DC:50V; Dielectric Characteristic:X7R; Package/Case:1206; Series:W3F; Leaded Process Compatible:Yes |
| Am29LV400BB70RWAE | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| Am29LV400BB70RWAEB | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV400BB70RWAC | Ceramic Multilayer Capacitor; Capacitor Type:General Purpose; Capacitance:22pF; Capacitance Tolerance:, -20%; Voltage Rating:100VDC; Capacitor Dielectric Material:Multilayer Ceramic; Package/Case:1206; Termination:SMD RoHS Compliant: Yes |
| AM29LV400BT70RWAC | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29LV400BB-120EC | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 4M-Bit 512K x 8/256K x 16 120ns 48-Pin TSOP |
| AM29LV400BB-120EI | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 4Mbit 512K/256K x 8bit/16bit 120ns 48-Pin TSOP |
| AM29LV400BB-120SC | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 4Mbit 512K/256K x 8bit/16bit 120ns 44-Pin SOP |
| AM29LV400BB-120WAI | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 4M-Bit 512K x 8/256K x 16 120ns 48-Pin FBGA |
| AM29LV400BB-55RWAI | 制造商:Spansion 功能描述:SPZAM29LV400BB-55RWAI 4M FLASH EOL150606 |
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