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参数资料
| 型号： | Am29LV400B-90RWAEB |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | CAP 0.47UF 50V +50-20% X7R SMD-0612 TR-7 PLATED-NI/SN HC-FEEDTHRU |
| 中文描述： | 4兆位（512亩x 8-Bit/256亩x 16位），3.0伏的CMOS只引导扇区闪存 |
| 文件页数： | 5/40页 |
| 文件大小： | 516K |
| 代理商： | AM29LV400B-90RWAEB |
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13
Am29LV400
PR EL IMIN AR Y
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The system must issue the reset command to re-ena-
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
See “AC Characteristics” for parameters, and to Figure
13 for the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements.
This method is an alternative to that shown in Table 4,
which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A
read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is unpro-
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is
not required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
5 shows the address and data requirements for the
byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
相关PDF资料 |
PDF描述 |
|---|---|
| Am29LV400BB70RWACB | Ceramic Multilayer Capacitor; Capacitance:470pF; Capacitance Tolerance:+50, -20 %; Working Voltage, DC:50V; Dielectric Characteristic:X7R; Package/Case:1206; Series:W3F; Leaded Process Compatible:Yes |
| Am29LV400BB70RWAE | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| Am29LV400BB70RWAEB | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV400BB70RWAC | Ceramic Multilayer Capacitor; Capacitor Type:General Purpose; Capacitance:22pF; Capacitance Tolerance:, -20%; Voltage Rating:100VDC; Capacitor Dielectric Material:Multilayer Ceramic; Package/Case:1206; Termination:SMD RoHS Compliant: Yes |
| AM29LV400BT70RWAC | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29LV400BB-120EC | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 4M-Bit 512K x 8/256K x 16 120ns 48-Pin TSOP |
| AM29LV400BB-120EI | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 4Mbit 512K/256K x 8bit/16bit 120ns 48-Pin TSOP |
| AM29LV400BB-120SC | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 4Mbit 512K/256K x 8bit/16bit 120ns 44-Pin SOP |
| AM29LV400BB-120WAI | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 4M-Bit 512K x 8/256K x 16 120ns 48-Pin FBGA |
| AM29LV400BB-55RWAI | 制造商:Spansion 功能描述:SPZAM29LV400BB-55RWAI 4M FLASH EOL150606 |
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