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| 型号： | AN-6003 |
| 厂商： | Fairchild Semiconductor Corporation |
| 英文描述： | Shoot-through in Synchronous Buck Converters |
| 中文描述： | 拍摄通过在同步降压转换器 |
| 文件页数： | 2/6页 |
| 文件大小： | 143K |
| 代理商： | AN-6003 |
Shoot-through in Synchronous Buck Regulators
AN-6003
04/25/2003
2
“Gate Step” – The shoot-
through culprit
If the adaptive circuits are working, then we
shouldn’t see any shoot-through, right
Not exactly. Most shoot-through occurs when the
high-side MOSFET is turned on. The high dv/dT on
the SW node (Drain of the low-side MOSFET)
couples charge through C
. This drives the gate
positive at the very moment when the driver is trying
to hold the gate low. C
and C
form a capacitive
voltage divider, which attenuates the gate step such
that the worst case peak amplitude of the gate step
(V
STEP
) seen is:
≈
+
)
C
C
(
R
T
R
IN
GD
T
)
PK
(
STEP
V
GS
GD
T
R
e
1
T
V
C
R
(1a)
Where R
= R
+ R
+ R
(see Figure 5),
and T
R
is the rise-time of the SW node.
The limiting case is when T
R
= 0. Then
GS
GD
GD
+
IN
)
MAX
(
STEP
V
C
C
C
V
≈
(1b)
This expression only illustrates the AC portion of the
gate step. The gate step is injected onto whatever
voltage the MOSFET’s gate has discharged to. For
example, if the switch node rises when VGS = 1V,
and the gate step amplitude is 2V, instantaneously
there will be 3 V
which is more than enough to
have a high instantaneous current through both
MOSFETs. It’s important, therefore that adaptive
gate drive circuits allow sufficient delay to prevent
the high side from turning on before the low-side V
GS
is discharged down to a few hundred mV.
An illustration of gate step is seen below.
0
1
2
3
4
5
6
0
20
40
60
80
t (nS)
V
G
-2
0
2
4
6
8
10
12
14
V
SW NODE VOLTAGE
LS MOSFET GATE
Figure 3. Gate Step for V
IN
.=12V.
0
1
2
3
4
5
6
0
20
40
60
80
t (nS)
V
G
-5
0
5
10
15
20
25
V
SW NODE VOLTAGE
LS MOSFET GATE
Figure 4. Gate Step for V
IN
.=20V
Further exacerbating the problem for adaptive
circuits is the fact that the adaptive comparator is not
actually sensing the voltage at the internal gate
junction of the MOSFET. As seen in Figure 5, the
internal MOSFET’s gate voltage has an unavoidable
internal R
resistance. In addition, some designers
like to have a “damping” resistor in series with the
gates of MOSFETs that are located physically far
away from their gate drives. This creates a bigger
problem for the adaptive gate drive circuit. These
series resistances form a voltage divider with the
internal pull-down resistance of the low-side gate
drive of the IC, causing it to think the gate voltage is
lower than it really is when it decides to release the
High-side driver.
R
DRIVER
R
Damping
H.S. MOSFET
1V
HDRV
LDRV
R
GATE
C
GS
C
GD
D
S
G
Q2
Delay
Figure 5. Resistance in the gate drive path
attenuates the voltage at the MOSFET gate node.
When there is 1V at the pin of the IC, the internal
MOSFET V
GS
is:
(
DRIVER
R
)
Damping
GATE
DRIVER
)
GS
R
R
R
V
1
V
+
+
=
Consider an example where:
R
DRIVER
= 2
,
R
DAMPING
= 5
R
GATE
= 1.2
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