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| 型号： | AN-6003 |
| 厂商： | Fairchild Semiconductor Corporation |
| 英文描述： | Shoot-through in Synchronous Buck Converters |
| 中文描述： | 拍摄通过在同步降压转换器 |
| 文件页数： | 4/6页 |
| 文件大小： | 143K |
| 代理商： | AN-6003 |
Shoot-through in Synchronous Buck Regulators
AN-6003
04/25/2003
4
Each of the MOSFETs represented is from a different
process and has different ratios of internal
capacitance.
MOSFET
V
STEP(MAX)
V
TH(MIN)
V
STEP
–V
TH(MIN)
0.53
0.02
0.14
0.78
0.21
I
PEAK
(max)
0.31
0.02
0.07
16.37
0.13
MOSFET1
MOSFET2
MOSFET3
MOSFET4
MOSFET5
1.53
0.82
1.14
1.78
0.81
1
0.8
1
1
0.6
Table 3. Maximum V
and I
@
V
IN
= 19V and V
GS(START)
= 0V.
Table 3 assumes that the V
has dropped to 0 before
the SW node rises when HDRV turns on. As
demonstrated above, the smallest amplitude of V
comes from MOSFET2 and MOSFET5, which are
low-threshold devices. Low threshold in large part is
due to a thin gate oxide, giving the MOSFET a high
C
ratio, which attenuates V
STEP
. more than other
GD
GS
C
MOSFETs.
Also, Table 3 only shows the theoretical peak current
in Q2 due to the gate step. In a real converter,
parasitic inductance limits the rise in current to
4A/nS. Even for the MOSFET4, the gate pulse only
stays above threshold for about 5nS, so the shoot-
through current would be further limited.
An additional shortcoming of the simplified
calculations of Table 3 is the assumption that SW
node turn-on begins when V
of the low-side is at 0.
As we saw from the earlier discussion, this may not
be the case.
Reducing gate step by slowing
down Q1 rise time
Usually, designers attempt to achieve the fastest rise-
time possible on the High-Side MOSFET in order to
minimize switching losses. A simplified expression
for turn-on losses (P
(TURN-ON)
) for the high-side
MOSFET is:
≈
2
I
V
T
F
P
OUT
IN
R
SW
ON
TURN
(3)
where T
R
is the rise-time of the MOSFET. A very
dV
on SW) is desirable to
fast rise-time (high
dt
minimize high-side power dissipation, but if it results
in a large gate-step, causing shoot-through, the
dissipation effect can be greater than the dissipation
induced by slowing the rise time. In some situations
this is the only practical approach to eliminate shoot-
through.
As can be seen in Figure 8, slowing down the rise
time has a dramatic effect on the amplitude of V
that is coupled into the Low-side MOSFET gate. T
slowdown has the added benefit of reducing EMI, but
comes at a cost of efficiency loss . Figure 8 and
subsequent tables were simulated with MOSFETs
typical of those used in notebook PC’s (2 in parallel)
with 15A output current and 19V
. Figure 8 assumes
that the SW node begins to rise when the internal
gate node has discharged down to 0.5V.
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