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参数资料
型号： APA300-FGG256I
厂商： Microsemi SoC
文件页数： 140/178页
文件大小： 0K
描述： IC FPGA PROASIC+ 300K 256-FBGA
标准包装： 90
系列： ProASICPLUS
RAM 位总计： 73728
输入/输出数： 186
门数： 300000
电源电压： 2.3 V ~ 2.7 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 256-LBGA
供应商设备封装： 256-FPBGA（17x17）
ProASICPLUS Flash Family FPGAs
2- 54
v5.9
Embedded Memory Specifications
This section discusses ProASICPLUS SRAM/FIFO embedded
memory and its interface signals, including timing
diagrams that show the relationships of signals as they
pertain to single embedded memory blocks (Table 2-51).
Table 2-13 on page 2-21 shows basic SRAM and FIFO
configurations. Simultaneous read and write to the same
location must be done with care. On such accesses the DI
bus is output to the DO bus. Refer to the ProASICPLUS
RAM and FIFO Blocks application note for more
information.
Enclosed Timing Diagrams—SRAM Mode:
"Synchronous SRAM Read, Access Timed Output
Strobe (Synchronous Transparent)" section on
page 2-55
"Synchronous SRAM Read, Pipeline Mode Outputs
(Synchronous Pipelined)" section on page 2-56
"Asynchronous SRAM Write" section on page 2-57
"Asynchronous SRAM Read, Address Controlled,
RDB=0" section on page 2-58
"Asynchronous SRAM Read, RDB Controlled"
section on page 2-58
"Synchronous SRAM Write"
Embedded Memory Specifications
The difference between synchronous transparent and
pipeline modes is the timing of all the output signals
from the memory. In transparent mode, the outputs will
change within the same clock cycle to reflect the data
requested by the currently valid access to the memory. If
clock cycles are short (high clock speed), the data
requires most of the clock cycle to change to valid values
(stable signals). Processing of this data in the same clock
cycle is nearly impossible. Most designers add registers at
all outputs of the memory to push the data processing
into the next clock cycle. An entire clock cycle can then
be used to process the data. To simplify use of this
memory
setup,
suitable
registers
have
been
implemented as part of the memory primitive and are
available to the user in the synchronous pipeline mode.
In this mode, the output signals will change shortly after
the second rising edge, following the initiation of the
read access.
Table 2-51 Memory Block SRAM Interface Signals
SRAM Signal
Bits
In/Out
Description
WCLKS
1
In
Write clock used on synchronization on write side
RCLKS
1
In
Read clock used on synchronization on read side
RADDR[0:7]
8
In
Read address
RBLKB
1
In
True read block select (active Low)
RDB
1
In
True read pulse (active Low)
WADDR[0:7]
8
In
Write address
WBLKB
1
In
Write block select (active Low)
DI[0:8]
9
In
Input data bits [0:8], [8] can be used for parity In
WRB
1
In
Negative true write pulse
DO[0:8]
9
Out
Output data bits [0:8], [8] can be used for parity Out
RPE
1
Out
Read parity error (active High)
WPE
1
Out
Write parity error (active High)
PARODD
1
In
Selects odd parity generation/detect when high, even when low
Note: Not all signals shown are used in all modes.
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相关代理商/技术参数
参数描述
APA300-FGG256M 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 256FBGA - Trays
APA300-FGGB 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA300-FGGES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA300-FGGI 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA300-FGGM 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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