参数资料
型号: APA450-FGG484A
厂商: Microsemi SoC
文件页数: 148/178页
文件大小: 0K
描述: IC FPGA PROASIC+ 450K 484-FBGA
标准包装: 40
系列: ProASICPLUS
RAM 位总计: 110592
输入/输出数: 344
门数: 450000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: -40°C ~ 125°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
ProASICPLUS Flash Family FPGAs
v5.9
2-61
Synchronous Write and Read to the Same Location
Note: * New data is read if WCLKS
occurs before setup time. The data stored is read if WCLKS occurs after hold time. The plot shows
the normal operation status.
Figure 2-34 Synchronous Write and Read to the Same Location
Table 2-58 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
WCLKRCLKS
WCLKS
↑ to RCLKS ↑ setup time
0.1
ns
WCLKRCLKH
WCLKS
↑ to RCLKS ↑ hold time
7.0
ns
OCH
Old DO valid from RCLKS
3.0
ns
OCA/OCH displayed for
Access Timed Output
OCA
New DO valid from RCLKS
7.5
ns
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write
clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS
and RCLKS driven by the same design signal.
3. If WCLKS changes after the hold time, the data will be read.
4. A setup or hold time violation will result in unknown output data.
RCLKS
DO
WCLKS
t
WCLKRCLKH
New Data*
Last Cycle Data
t
WCLKRCLKS
t
OCH
t
CCYC
t
CMH
t
CML
t
OCA
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