参数资料
型号: AS1369-BWLT-33
厂商: ams
文件页数: 15/22页
文件大小: 0K
描述: IC REG LDO 3.3V .2A 4WLCSP
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 3.3V
输入电压: 最高 5.5V
电压 - 压降(标准): 0.08V @ 200mA
稳压器数量: 1
电流 - 输出: 200mA
电流 - 限制(最小): 210mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 4-UFBGA,WLCSP
供应商设备封装: 4-WLCSP
包装: 标准包装
其它名称: AS1369-BWLT-33DKR
AS1369
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 47. Graphical Representation of Dropout Voltage
V IN
V OUT
V IN =V OUT(TYP) +0.5V
Dropout
V IN
Voltage
V OUT
100mV
V OUT
V IN
Figure 47 shows the variation of V OUT as V IN is varied for a certain load current. The practical value of dropout is the differential voltage (V OUT
- V IN ) measured at the point where the LDO output voltage has fallen by 100mV below the nominal, fully regulated output value. The nominal
regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential.
8.2 Efficiency
Low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the regulator efficiency is
directly related to quiescent current and dropout voltage. Efficiency is given by:
V LOAD ? I LOAD
V IN ? I Q + I LOAD ?
Efficiency = ----------------------------------------- ? 100 %
(EQ 3)
Where:
IQ = Quiescent current of LDO
8.3 Power Dissipation
Maximum power dissipation (PD) of the LDO is the sum of the power dissipated by the internal series MOSFET and the quiescent current
required to bias the internal voltage reference and the internal error amplifier, and is calculated as:
PD ? MAX ? ? Seriespass ? = I LOAD ? MAX ? ? V IN ? MAX ? – V OUT ? MIN ? ? Watts
Internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calculated as:
PD ? MAX ? ? Bias ? = V IN ? MAX ? I Q Watts
Total LDO power dissipation is calculated as:
PD ? MAX ? ? Total ? = PD ? MAX ? ? Seriespass ? + PD ? MAX ? ? Bias ? Watts
(EQ 4)
(EQ 5)
(EQ 6)
www.austriamicrosystems.com/LDOs/AS1369
Revision 1.7
14 - 21
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