参数资料
型号: AS3543-ECTP
厂商: ams
文件页数: 73/92页
文件大小: 0K
描述: IC CODEC AUDIO FRONT END 68CTBGA
标准包装: 4,000
类型: 音频编解码器
应用: 便携式音频,电话
安装类型: 表面贴装
封装/外壳: 68-TFBGA
供应商设备封装: 68-CTBGA(6x6)
包装: 带卷 (TR)
www.austriamicrosystems.com
Revision 1.11
74 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 74. PLL Register
Name
Base
Default
PLL
2-wire serial
00h
Offset: 1Ah-7
PLL Register
This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7:4
OSR<3:0>
0000
R/W
Sets the oversampling rate when using the internal PLL
0x0: 128
0x1-0xF: n/a
3:2
VCO_MODE<1:0>
00
R/W
Selects the speed of the PLL VCO according to the audio
sampling frequency.
00: normal: 24-48kHz
01: low: 8-23kHz
10: high: 49-96kHz
11: n/a
1:0
PLL_MODE<1:0>
00
R/W
Selects the PLL mode and master clock frequency source
00: automatic
turns PLL on, PLL clock is used as master clock if freq(LRCK)
>8kHz and freq(MCLK)<32*freq(LRCK)
01: ON; turns PLL on, PLL clock is used as master clock
10: OFF; turns the PLL off, MCLK is used as master clock
11: auto_inv; like automatic but with inverted clock
Table 75. DCDC15 Register
Name
Base
Default
DCDC15
2-wire serial
00h
Offset: 1Bh-1
DCDC15 Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7
DIM_UP_XDOWN
0
R/W
0: disables the step-up converter and dims it down
1: enables the step-up converter and dims it up
6:5
DIM_RATE<1:0>
00
R/W
Selects the dimming speed when enabling or disablilng the
DCDC15
00: 0ms
01: 300ms
10: 600ms
11: 1200ms
4
VFB_ON
0
R/W
0: current feedback selected via ISINK1 and ISINK2
1: voltage feedback selected, ISINK1 is sinking 50uA to define
the voltage via an external zener diode
3
ExtDim_ON
0
R/W
0: selects internal clock for dimming
1: selects external clock for dimming
2:0
-
000
n/a
ams
AG
Technical
content
still
valid
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