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参数资料
| 型号： | AS5SS128K36DQ-12/XT |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| 中文描述： | 128K X 36 ZBT SRAM, 9 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 14/16页 |
| 文件大小： | 119K |
| 代理商： | AS5SS128K36DQ-12/XT |
SSRAM
AS5SS128K36
AS5SS128K36
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
Austin Semiconductor, Inc.
TRUTH TABLE (5-10)
NOTE:
1.
CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ
or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a
DESELECT cycle is first executed.
2.
DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.
A WRITE ABORT means a WRITE command is given, but no operation is performed.
3.
OE\ may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. OE\ may be used when the bus turn-on and turn-off times do not meet an applications
requirements.
4.
If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK
EDGE cycle.
5.
X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa\, BWb\, BWc\,
BWd\) are HIGH. BWx = L means all byte write signals are LOW.
6.
BWa\ enables WRITES to Byte “a” (DQa pins); BWb\ enables WRITES to Byte “b” (DQb pins); BWc\ enables WRITES to
Byte “c” (DQc pins); BWd\ enables WRITES to Byte “d” (DQd pins).
7.
All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8.
Wait states are inserted by setting CKE\ HIGH.
9.
This device contains circuitry that will ensure that the outputs will be in the High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
OPERATION
ADDRESS
USED
CE\
CE2\ CE2
ZZ ADV/LD\ R/W\ BWx OE\ CKE\
CLK
DQ
NOTES
DESELECT CYCLE
None
H
X
L
X
L
H
High-Z
DESELECT CYCLE
None
X
H
X
L
X
L
H
High-Z
DESELECT CYCLE
None
X
L
X
L
H
High-Z
CONTINUE DESELECT CYCLE
None
X
L
H
X
L
H
High-Z
1
READ CYCLE
(Begin Burst)
External
L
H
L
H
X
L
HQ
READ CYCLE
(Continue Burst)
Next
X
L
H
X
L
HQ
1, 11
NOP/DUMMY READ
(Begin Burst)
External
L
H
L
H
X
H
L
H
High-Z
2
DUMMY READ
(Continue Burst)
Next
X
L
H
X
H
L
H
High-Z 1, 2, 11
WRITE CYCLE
(Begin Burst)
External
L
H
L
X
L
HD
3
WRITE CYCLE
(Continue Burst)
Next
X
L
H
X
L
X
L
H
D
1, 3, 11
NOP/WRITE ABORT
(Begin Burst)
None
L
H
L
H
X
L
H
High-Z
2, 3
WRITE ABORT
(Continue Burst)
Next
X
L
H
X
H
X
L
H
High-Z
1, 2, 3,
11
IGNORE CLOCK EDGE
(Stall)
Current
X
L
X
H
L
H
---
4
SNOOZE MODE
None
X
H
X
High-Z
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