参数资料
型号: AS5SS256K18DQ-8IT
厂商: Austin Semiconductor, Inc
英文描述: 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through
中文描述: 256 × 18的SSRAM同步突发静态存储器,流通过
文件页数: 1/13页
文件大小: 225K
代理商: AS5SS256K18DQ-8IT
AS5SS256K18
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
FEATURES
Fast access times: 8, 10, and 15ns
Fast clock speed: 113, 100, and 66 MHz
Fast clock and OE\ access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRTIE control and GLOBAL WRITE
Three chip enables for simple depth expansion and address
pipelining
Clock-controlled and registered addresses, data I/Os and
control signals
Interally self-timed WRITE cycle
Burst control pin (interleaved or linear burst)
Automatic power-down
Low capacitive bus loading
Operating Temperature Ranges:
- Military -55oC to +125oC
- Industrial -40oC to +85oC
OPTIONS
MARKING
Timing
7.5ns/8ns/113 MHz
-8*
8.5ns/10ns/100 MHz
-9
10ns/15ns/66 MHz
-10
Packages
100-pin TQFP
DQ
No. 1001
Operating Temperature Ranges:
- Military -55oC to +125oCIT
- Industrial -45oC to +85oCXT
*available as IT only.
256K x 18 SSRAM
Synchronous Burst SRAM,
Flow-Through
PIN ASSIGNMENT
(Top View)
100-pin TQFP
For more products and information
please visit our web site at
www.austinsemiconductor.com
SA
CE\
CE2
NC
bwB\
BWa\
CE2\
V
DD
V
SS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA SA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
VDDQ
VSS
NC
DQb
VSS
VDDQ
DQb
VSS
VDD
NC
VSS
DQb
V
DDQ
VSS
DQb
DQPb
NC
VSS
VDDQ
NC
SA
NC
VDDQ
VSS
NC
DQPa
DQa
VSS
VDDQ
DQa
VSS
NC
VDD
ZZ
DQa
VDDQ
VSS
DQa
NC
VSS
VDDQ
NC
MODE
SA
1
SA
0
DNU
V
SS
V
DD
NF**
SA
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. Synchronous Burst SRAM family
employs high-speed, low power CMOS designs that are fabricated us-
ing an advanced CMOS process.
ASI’s 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM
core with advanced synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE\), two additional chip enables for easy depth expansion (CE2\,
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\).
Asynchronous inputs include the output enable (OE\), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE) that
selects between interleaved and linear burst modes. The data-out (Q),
enabled by OE\, is also asynchronous. WRITE cycles can be from one
to two bytes wide, as controlled by the write control inputs.
Burst operation can be initiated with either address status processor
(ADSP\) or address status controller (ADSC\) inputs. Subsequent burst
addresses can be internally generated as controlled by the burst ad-
vance input (ADV\).
Address and write control are registered on-chip to simplify WRITE
cycles. This allows self-timed WRITE cycles. Individual byte enables
allow individual bytes to be written. During WRITE cycles on this x18
device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins
and DQPb. GW\ LOW causes all bytes to be written. Parity bits are
available on this device.
ASI’s 4Mb Synchronous Burst SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are TTL-compatible. The de-
vice is ideally suited for 486, Pentium, and PowerPC systems and
those systems that benefit from a wide synchronous data bus.
**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
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