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参数资料
| 型号： | AS5SS256K36ADQ-8.5/883C |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
| 中文描述： | 256K X 36 STANDARD SRAM, 8.5 ns, PQFP100 |
| 封装： | 14 X 20 MM, 1.40 MM HEIGHT, MS-026, TQFP-100 |
| 文件页数： | 1/16页 |
| 文件大小： | 391K |
| 代理商： | AS5SS256K36ADQ-8.5/883C |
SSRAM
AS5SS256K36 &
AS5SS256K36A
AS5SS256K36 &
AS5SS256K36A
Rev. 3.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
Austin Semiconductor, Inc.
For more products and information
please visit our web site at
www.austinsemiconductor.com
256K x 36 SSRAM
Flow-Through, Synchronous
Burst SRAM
FEATURES
Organized 256K x 36
Fast Clock and OE\ access times
Single +3.3V +0.3V/-0.165V power supply (V
DD)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and address
pipelining
Clock-controlled and registered addresses, data I/Os and
control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP package for high density, high speed
Low capacitive bus loading
OPTIONS
MARKING
Timing
8.5ns/10ns/100MHz
-8.5*
10ns/15ns/66MHz
-10
Packages
100-pin TQFP (2-chip enable)
DQ No. 1001
Pinout
2-chip Enables
A (PRELIMINARY)
3-chip Enables
no indicator
Operating Temperature Ranges
Military (-55oC to +125oC)
XT*
Industrial (-40oC to +85oC)
IT
*NOTE: -8.5/XT combination not available.
PIN ASSIGNMENT
(Top View)
100-pin TQFP (DQ)
(2-chip enable version, “A” indicator)
100-pin TQFP (DQ)
(3-chip enable version, no indicator)
GENERAL DESCRIPTION
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x 36
SRAM core with advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK). The synchro-
nous inputs include all addresses, all data inputs, active LOW chip en-
able (CE\), two additional chip enables for easy depth expansion (CE2\,
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\). Note that CE2\ is not available on the
A version.
DQPc
DQc
VDDQ
Vss
DQc
Vss
VDDQ
DQc
Vss
VDD
NC
Vss
DQd
VDDQ
Vss
DQd
Vss
VDDQ
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
VDDQ
Vss
DQb
Vss
VDDQ
DQb
Vss
NC
VDD
ZZ
DQa
VDDQ
Vss
DQa
Vss
VDDQ
DQa
DQPa
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
NF
V
DD
Vss
DNU
SA0
SA1
SA
MODE
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
CE2\
BW
a
\
BWb\
BWc\
BWd\
CE2
CE\
SA
DQPc
DQc
VDDQ
Vss
DQc
Vss
VDDQ
DQc
Vss
VDD
NC
Vss
DQd
VDDQ
Vss
DQd
Vss
VDDQ
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
VDDQ
Vss
DQb
Vss
VDDQ
DQb
Vss
NC
VDD
ZZ
DQa
VDDQ
Vss
DQa
Vss
VDDQ
DQa
DQPa
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
NF
V
DD
Vss
DNU
SA0
SA1
SA
MODE
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
SA
BW
a
\
BWb\
BWc\
BWd\
CE2
CE\
SA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS5SS256K36DQ10 | 制造商:ASI 功能描述:NEW |
| AS5SS256K36DQ-10/883C | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
| AS5SS256K36DQ-10/IT | 制造商:Micross Components 功能描述:SSRAM-FT, 9.0MB - Trays |
| AS5SS256K36DQ-10/XT | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
| AS5SS256K36DQ-8.5/883C | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
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