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参数资料
| 型号： | AS5SS256K36ADQ-8.5/883C |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
| 中文描述： | 256K X 36 STANDARD SRAM, 8.5 ns, PQFP100 |
| 封装： | 14 X 20 MM, 1.40 MM HEIGHT, MS-026, TQFP-100 |
| 文件页数： | 16/16页 |
| 文件大小： | 391K |
| 代理商： | AS5SS256K36ADQ-8.5/883C |
SSRAM
AS5SS256K36 &
AS5SS256K36A
AS5SS256K36 &
AS5SS256K36A
Rev. 3.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (-55oC to +125oC or -40oC to +85oC)
MIN
MAX
MIN
MAX
CLOCK
Clock cycle time
tKC
10.0
15.0
ns
Clock frequency
tKF
100
66
MHz
Clock HIGH time
tKH
3.0
4.0
ns
2
Clock LOW time
tKL
3.0
4.0
ns
2
OUTPUT TIMES
Clock to output valid
tKQ
8.5
10.0
ns
Clock to output invalid
tKQX
3.0
ns
3
Clock to output in Low-Z
tKQLZ
3.0
ns
3, 4, 5, 6,
Clock to output in High-Z
tKQHZ
5.0
ns
3, 4, 5, 6,
OE\ to output valid
tOEQ
5.0
ns
7
OE\ to output in Low-Z
tOELZ
0
ns
3, 4, 5, 6,
OE\ to output in High-Z
tOEHZ
5.0
ns
3, 4, 5, 6,
SETUP TIMES
Address
tAS
1.8
2.0
ns
8, 9
Address status (ADSC\, ADSP\)
tADSS
1.8
2.0
ns
8, 9
Address advance (ADV\)
tAAS
1.8
2.0
ns
8, 9
Byte write enables (BWa\ - BWd\, GW\, BWE\)
tWS
1.8
2.0
ns
8, 9
Data-in
tDS
1.8
2.0
ns
8, 9
Chip enable (CE\)
tCES
1.8
2.0
ns
8, 9
HOLD TIMES
Address
tAH
0.5
ns
8, 9
Address status (ADSC\, ADSP\)
tADSH
0.5
ns
8, 9
Address advance (ADV\)
tAAH
0.5
ns
8, 9
Byte write enables (BWa\ - BWd\, GW\, BWE\)
tWH
0.5
ns
8, 9
Data-in
tDH
0.5
ns
8, 9
Chip enable (CE\)
tCEH
0.5
ns
8, 9
UNITS
NOTES
SYMBOL
DESCRIPTION
-10
-8.5
NOTE:
1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
2. Measured as HIGH above V
IH
and LOW below V
IL
.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.
4. This parameter is sampled.
5. Transition is measured +500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these
parameters.
7. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.
8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by
a t
least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or
ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges
of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to
remain enabled.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS5SS256K36DQ10 | 制造商:ASI 功能描述:NEW |
| AS5SS256K36DQ-10/883C | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
| AS5SS256K36DQ-10/IT | 制造商:Micross Components 功能描述:SSRAM-FT, 9.0MB - Trays |
| AS5SS256K36DQ-10/XT | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
| AS5SS256K36DQ-8.5/883C | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
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