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参数资料
| 型号： | AS5SS256K18DQ-8IT |
| 厂商： | Austin Semiconductor, Inc |
| 英文描述： | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| 中文描述： | 256 × 18的SSRAM同步突发静态存储器，流通过 |
| 文件页数： | 8/13页 |
| 文件大小： | 225K |
| 代理商： | AS5SS256K18DQ-8IT |
AS5SS256K18
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
TRUTH TABLE
NOTES: 1. X means “Don’t Care.” \ means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\) and BWE\ are LOW or GW\ is LOW. WRITE\ = H for a ll BWx\,
BWE\, GW\ HIGH.
3. BWa\ enables WRITEs to DQas and DQPa. BWb\ enables WRITEs to DQbs and DQPb.
4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH throughout the input
data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals
and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
OPERATION
ADDRESS
USED
CE\
CE2\ CE2
ZZ ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK
DQ
DESELECT Cycle, Power-Down
NONE
H
X
L
X
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
NONE
L
X
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
NONE
L
H
X
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
NONE
L
X
L
H
L
X
L-H
High-Z
DESELECT Cycle, Power-Down
NONE
L
H
X
L
H
L
X
L-H
High-Z
SNOOZE MODE, Power-Down
NONE
X
H
X
High-Z
READ Cycle, Begin Burst
EXTERNAL
L
H
L
X
L
L-H
Q
READ Cycle, Begin Burst
EXTERNAL
L
H
L
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
EXTERNAL
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
EXTERNAL
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
EXTERNAL
L
H
L
H
L
X
H
L-H
High-Z
READ Cycle, Continue Burst
NEXT
X
L
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
NEXT
X
L
H
L
H
L-H
High-Z
READ Cycle, Continue Burst
NEXT
H
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
NEXT
H
X
L
X
H
L
H
L-H
High-Z
WRITE Cycle, Continue Burst
NEXT
X
L
H
L
X
L-H
D
WRITE Cycle, Continue Burst
NEXT
H
X
L
X
H
L
X
L-H
D
READ Cycle, Suspend Burst
CURRENT
X
L
H
L
L-H
Q
READ Cycle, Suspend Burst
CURRENT
X
L
H
L-H
High-Z
READ Cycle, Suspend Burst
CURRENT
H
X
L
X
H
L
L-H
Q
READ Cycle, Suspend Burst
CURRENT
H
X
L
X
H
L-H
High-Z
WRITE Cycle, Suspend Burst
CURRENT
X
L
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
CURRENT
H
X
L
X
H
L
X
L-H
D
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS5SS256K18DQ-9 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x18 Fast Synchronous SRAM |
| AS5SS256K18DQ-9/IT | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-9/XT | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K36 | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
| AS5SS256K36_05 | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM |
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