- 您现在的位置：买卖IC网 > PDF目录166232 > AS5SS128K36DQ-12/XT (AUSTIN SEMICONDUCTOR INC) 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT PDF资料下载
参数资料
| 型号： | AS5SS128K36DQ-12/XT |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT |
| 中文描述： | 128K X 36 ZBT SRAM, 9 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 9/16页 |
| 文件大小： | 119K |
| 代理商： | AS5SS128K36DQ-12/XT |
SSRAM
AS5SS128K36
AS5SS128K36
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Austin Semiconductor, Inc.
PIN ASSIGNMENT
(Top View)
100-pin TQFP (DQ)
PIN DESCRIPTIONS
TQFP PINS
SYMBOL
TYPE
DESCRIPTION
37
36
32-35, 44-50,
81, 82, 99, 100
SA0
SA1
SA
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as
address bits for the higher-density 8Mb and 16Mb ZBL SRAMs, respectively. SA0 and
SA1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
93
94
95
96
BWa\
BWb\
BWc\
BWd\
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to
be written when a WRITE cycle is active and must meet the setup and hold times
around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle
as the address. BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls
DQc pins; BWd\ controls DQd pins.
87
CKE\
Input
Synchronous Clock Enable:
This active LOW input permits CLK to propagate
throughout the device. When CKE is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This input must meet setup and
hold times around the rising edge of CLK.
88
R/W\
Input
Read/Write: This input determines the cycle type when ADV/LD\ is LOW and is the
only means for determining READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin
permits BYTE WRITE operations and must meet the setup and hold times around the
rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQc
V
DD
Q
V
SS
DQc
V
SS
V
DD
Q
DQc
V
SS
V
DD
V
DD
V
SS
DQd
V
DD
Q
V
SS
DQd
V
SS
V
DD
Q
DQd
DQb
V
DD
Q
V
SS
DQb
V
SS
V
DD
Q
DQb
V
SS
V
SS
V
DD
ZZ
DQa
V
DD
Q
V
SS
DQa
V
SS
V
DD
Q
DQa
MODE
(LBO\)
SA
SA1
SA0
DNU
V
SS
V
DD
DNU
SA
CE\
CE2
BWd\
BWc\
BWb\
BWa\
CE2\
V
DD
V
S
CLK
R/W\
CKE\
OE\
(G\)
ADV/LD\
NF
SA
相关PDF资料 |
PDF描述 |
|---|---|
| AS5SS256K18DQ-10/IT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-10/XT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-9/IT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-9/XT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DQ-8IT | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AS5SS128K36DQ-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x36 Fast Synchronous SRAM |
| AS5SS128K36DQ-9 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x36 Fast Synchronous SRAM |
| AS5SS256K18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256K x 18 SSRAM Synchronous Burst SRAM. Flow-Through |
| AS5SS256K18_05 | 制造商:AUSTIN 制造商全称:Austin Semiconductor 功能描述:256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| AS5SS256K18DB-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x18 Fast Synchronous SRAM |
发布紧急采购，3分钟左右您将得到回复。